ics_publications_long.bib
@book{HGD:2024,
title = {Erweiterte virtuelle Prototypen f\"ur heterogene Systeme},
publisher = {Springer},
author = {Muhammad Hassan and Daniel Gro{\ss}e and Rolf Drechsler},
year = 2024,
doi = {10.1007/978-3-031-53152-1}
}
@book{MGD:2023,
title = {Formal Verification of Structurally Complex Multipliers},
publisher = {Springer},
author = {Alireza Mahzoon and Daniel Gro{\ss}e and Rolf Drechsler},
year = 2023,
doi = {10.1007/978-3-031-24571-8}
}
@book{HGD:2023,
title = {Verbessertes virtuelles Prototyping: Mit {RISC-V}-Fallstudien},
publisher = {Springer},
author = {Vladimir Herdt and Daniel Gro{\ss}e and Rolf Drechsler},
year = 2023,
doi = {10.1007/978-3-031-18174-0}
}
@book{HGD:2022,
title = {Enhanced Virtual Prototyping for Heterogeneous Systems},
publisher = {Springer},
author = {Muhammad Hassan and Daniel Gro{\ss}e and Rolf Drechsler},
year = 2022,
doi = {10.1007/978-3-031-05574-4}
}
@book{DG:2021,
title = {Recent Findings in Boolean Techniques},
publisher = {Springer},
editor = {Rolf Drechsler and Daniel Gro{\ss}e},
year = 2021,
doi = {10.1007/978-3-030-68071-8}
}
@book{HGD:2020e,
title = {Enhanced Virtual Prototyping: Featuring {RISC-V} Case Studies},
publisher = {Springer},
author = {Vladimir Herdt and Daniel Gro{\ss}e and Rolf Drechsler},
year = 2020,
doi = {10.1007/978-3-030-54828-5}
}
@book{KSG:2020,
title = {Languages, Design Methods, and Tools for Electronic System Design -- Selected Contributions from FDL 2018},
publisher = {Springer},
editor = {Tom J. Kazmierski and Sebastian Steinhorst and Daniel Gro{\ss}e},
year = 2020,
doi = {10.1007/978-3-030-31585-6}
}
@book{GVP:2019,
title = {Languages, Design Methods, and Tools for Electronic System Design -- Selected Contributions from FDL 2017},
publisher = {Springer},
editor = {Daniel Gro{\ss}e and Sara Vinco and Hiren Patel},
year = 2019,
doi = {10.1007/978-3-030-02215-0}
}
@book{CGD:2018,
title = {Design Automation Techniques for Approximation Circuits},
publisher = {Springer},
author = {Arun Chandrasekharan and Daniel Gro{\ss}e and Rolf Drechsler},
year = 2018,
doi = {10.1007/978-3-319-98965-5}
}
@book{GD:2017,
title = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen},
publisher = {Shaker Verlag},
editor = {Daniel Gro{\ss}e and Rolf Drechsler},
year = 2017
}
@proceedings{GB:2011,
editor = {Daniel Gro{\ss}e and Oliver Bringmann},
title = {8. Workshop Cyber-Physical Systems - Enabling Multi-Nature Systems: dom\"anen\"ubergreifender Entwurf von heterogenen eingebetteten Systemen, 23.-24. Februar 2011},
publisher = {Universit\"at Bremen},
year = {2011}
}
@book{GD:2010,
title = {Quality-Driven {SystemC} Design},
publisher = {Springer},
author = {Daniel Gro{\ss}e and Rolf Drechsler},
year = 2010,
doi = {10.1007/978-90-481-3631-5}
}
@book{GSD:2008,
title = {EXplayN - Strategieoptimierung und Analyse ausgew\"ahlter Spielprobleme},
publisher = {Shaker Verlag},
editor = {Daniel Gro{\ss}e and Andr\'e S\"ulflow and Nicole Drechsler},
year = 2008
}
@book{GFD:2007,
title = {SATRIX - Algorithmen f\"ur Boolesche Erf\"ullbarkeit},
publisher = {Shaker Verlag},
editor = {Daniel Gro{\ss}e and G\"orschwin Fey and Rolf Drechsler},
year = 2007
}
@incollection{HVE+:2023,
author = {Muhammad Hassan and Thilo V\"ortler and Karsten Einwich and Rolf Drechsler and Daniel Gro{\ss}e},
editor = {Drechsler, Rolf and Huhn, Sebastian},
title = {Toward System-Level Assertions for Heterogeneous Systems},
booktitle = {Advanced Boolean Techniques: Selected Papers from the 15th International Workshop on Boolean Problems},
year = 2023,
publisher = {Springer},
pages = {67--81},
doi = {10.1007/978-3-031-28916-3_5}
}
@incollection{MGD:2021b,
author = {Alireza Mahzoon and Daniel Gro{\ss}e and Rolf Drechsler},
title = {{GenMul}: Generating Architecturally Complex Multipliers to Challenge Formal Verification Tools},
booktitle = {Recent Findings in Boolean Techniques},
editor = {Rolf Drechsler and Daniel Gro{\ss}e},
publisher = {Springer},
pages = {177--191},
year = 2021,
doi = {10.1007/978-3-030-68071-8_9}
}
@incollection{HGLD:2020,
title = {Extensible and Configurable {RISC-V} based Virtual Prototype},
author = {Vladimir Herdt and Daniel Gro{\ss}e and Hoang M. Le and Rolf Drechsler},
booktitle = {Languages, Design Methods, and Tools for Electronic System Design: Selected Contributions from FDL 2018},
editor = {Tom J. Kazmierski and Sebastian Steinhorst and Daniel Gro{\ss}e},
publisher = {Springer},
pages = {115--134},
year = 2020,
doi = {10.1007/978-3-030-31585-6_7}
}
@incollection{FGD:2019c,
title = {Approximate Memory: Data Storage in the Context of Approximate Computing},
author = {Saman Froehlich and Daniel Gro{\ss}e and Rolf Drechsler},
booktitle = {Information Storage},
editor = {Cornelia S. Gro{\ss}e and Rolf Drechsler},
publisher = {Springer},
pages = {111--133},
year = 2019,
doi = {10.1007/978-3-030-19262-4_4}
}
@incollection{FGD:2019b,
title = {Approximate Hardware Generation Using Formal Techniques},
author = {Saman Froehlich and Daniel Gro{\ss}e and Rolf Drechsler},
booktitle = {Approximate Circuits: Methodologies and CAD},
editor = {Sherief Reda and Muhammad Shafique},
publisher = {Springer},
pages = {155--174},
year = 2019,
doi = {10.1007/978-3-319-99322-5_8}
}
@incollection{HLGD:2019b,
title = {Towards Early Validation of Firmware-Based Power Management using Virtual Prototypes: A Constrained Random Approach},
author = {Vladimir Herdt and Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler},
booktitle = {Languages, Design Methods, and Tools for Electronic System Design: Selected Contributions from FDL 2017},
editor = {Daniel Gro{\ss}e and Sara Vinco and Hiren Patel},
publisher = {Springer},
pages = {25--44},
year = 2019,
doi = {10.1007/978-3-030-02215-0_2}
}
@incollection{HLGD:2018b,
title = {On the Application of Formal Fault Localization to Automated {RTL-to-TLM} Fault Correspondence Analysis for Fast and Accurate {VP}-based Error Effect Simulation - A Case Study},
author = {Vladimir Herdt and Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler},
booktitle = {Languages, Design Methods, and Tools for Electronic System Design: Selected Contributions from FDL 2016},
editor = {F. Fummi and R. Wille},
publisher = {Springer},
pages = {39--58},
year = 2018,
doi = {10.1007/978-3-319-62920-9_3}
}
@incollection{GLD:2016b,
author = {Daniel Gro{\ss}e and Hoang M. Le and Rolf Drechsler},
title = {Formal Verification of {SystemC}-based Cyber Components},
booktitle = {Industrial Internet of Things: Cybermanufacturing Systems},
editor = {S. Jeschke and C. Brecher and H. Song and D. B. Rawat},
publisher = {Springer},
pages = {137--167},
year = {2016},
doi = {10.1007/978-3-319-42559-7_6}
}
@incollection{GFD:2011,
author = {Daniel Gro{\ss}e and G\"orschwin Fey and Rolf Drechsler},
title = {Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis},
booktitle = {Design and Test Technology for Dependable Systems-on-Chip},
editor = {R. Ubar and J. Raik and H. T. Vierhaus},
publisher = {Information Science Reference},
pages = {119--129},
year = 2011,
doi = {10.14279/tuj.eceasst.62.860}
}
@incollection{WGHD:2010,
author = {Robert Wille and Daniel Gro{\ss}e and Finn Haedicke and Rolf Drechsler},
title = {{SMT}-based Stimuli Generation in the {SystemC} Verification Library},
booktitle = {Advances in Design Methods from Modeling Languages for Embedded Systems and SoC's: Selected Contributions on Specification, Design, and Verification from FDL 2009},
editor = {D. Borrione},
publisher = {Springer},
pages = {227--244},
year = 2010,
doi = {10.1007/978-90-481-9304-2_14}
}
@incollection{Gro:2009,
author = {Daniel Gro{\ss}e},
title = {{Qualit\"atsorientierter Entwurfs- und Verifikationsablauf f\"ur digitale Systeme}},
booktitle = {Ausgezeichnete Informatikdisserationen 2008},
editor = {D. Wagner et al.},
publisher = {Gesellschaft f\"ur Informatik},
volume = {D-9},
series = {Lecture Notes in Informatics},
pages = {121--130},
year = 2009
}
@incollection{GWSD:2009,
author = {Daniel Gro{\ss}e and Robert Wille and Robert Siegmund and Rolf Drechsler},
title = {Debugging Contradictory Constraints in Constraint-based Random Simulation},
booktitle = {Languages for Embedded Systems and their Applications: Selected Contributions on Specification, Design, and Verification from FDL'08},
editor = {M. Radetzki},
publisher = {Springer},
pages = {273--290},
year = 2009,
doi = {10.1007/978-1-4020-9714-0_18}
}
@incollection{WFG+:2009,
author = {Robert Wille and G\"orschwin Fey and Daniel Gro{\ss}e and Stephan Eggersgl\"u{\ss} and Rolf Drechsler},
title = {SWORD: A {SAT} like Prover using Word Level Information},
booktitle = {VLSI-SoC: Advanced Topics on Systems on a Chip: A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip},
editor = {R. Reis and V. Mooney and P. Hasler},
pages = {175--192},
publisher = {Springer},
year = 2009,
doi = {10.1007/978-0-387-89558-1_10}
}
@incollection{GPKD:2008,
author = {Daniel Gro{\ss}e and Hernan Peraza and Wolfgang Klingauf and Rolf Drechsler},
title = {Measuring the Quality of a {SystemC} Testbench by using Code Coverage Techniques},
booktitle = {Embedded Systems Specification and Design Languages: Selected contributions from FDL'07},
editor = {E. Villar},
pages = {73--86},
publisher = {Springer},
year = 2008,
doi = {10.1007/978-1-4020-8297-9_6}
}
@incollection{GSD:2006,
author = {Daniel Gro{\ss}e and Robert Siegmund and Rolf Drechsler},
title = {Processor Verification},
booktitle = {Customizable Embedded Processors},
editor = {P. Ienne and R. Leupers},
publisher = {Elsevier},
pages = {281--302},
year = 2006,
doi = {10.1016/B978-012369526-0/50013-9}
}
@incollection{DG:2006,
author = {Rolf Drechsler and Daniel Gro{\ss}e},
title = {System-level validation using formal techniques},
booktitle = {System-on-Chip: Next Generation Electronics},
editor = {Bashir M. Al-Hashimi},
publisher = {The IEE},
pages = {715--745},
year = 2006
}
@article{HSG:2025,
author = {Christoph Hazott and Florian St\"ogm\"uller and Daniel Gro{\ss}e},
journal = {Integr.},
title = {Using Virtual Prototypes and Metamorphic Testing to Verify the Hardware/Software-Stack of Embedded Graphics Libraries},
volume = {101},
year = {2025},
code = {https://github.com/ics-jku/mt-graphlib-framework},
doi = {10.1016/j.vlsi.2024.102320}
}
@article{KSM+:2024,
author = {Alexander Konrad and Christoph Scholl and Alireza Mahzoon and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Divider verification using symbolic computer algebra and delayed don't care optimization: theory and practical implementation},
journal = {Formal Methods in System Design: An International Journal},
year = {2024},
month = {May},
doi = {10.1007/s10703-024-00452-3}
}
@article{KG:2024c,
author = {Lucas Klemmer and Daniel Gro{\ss}e},
title = {{WAVING} Goodbye to Manual Waveform Analysis in {HDL} Design with {WAL}},
journal = {IEEE Transactions on Computer Aided Design of Circuits and Systems},
year = {2024},
volume = {43},
number = {10},
pages = {3198--3211},
url = {https://ieeexplore.ieee.org/document/10496480},
doi = {10.1109/TCAD.2024.3387312}
}
@article{MGD:2022,
author = {Alireza Mahzoon and Daniel Gro{\ss}e and Rolf Drechsler},
title = {{RevSCA-2.0:} {SCA}-based Formal Verification of Non-trivial Multipliers using Reverse Engineering and Local Vanishing Removal},
journal = {IEEE Transactions on Computer Aided Design of Circuits and Systems},
year = {2022},
volume = {41},
number = {5},
pages = {1573-1586},
url = {https://ieeexplore.ieee.org/document/9440537},
doi = {10.1109/TCAD.2021.3083682}
}
@article{BHGD:2021,
author = {Niklas Bruns and Vladimir Herdt and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Toward {RISC-V} {CSR} Compliance Testing},
journal = {IEEE Embedded Systems Letters},
volume = {13},
number = {4},
pages = {202--205},
year = 2021,
doi = {10.1109/LES.2021.3077368}
}
@article{HGTD:2021,
author = {Vladimir Herdt and Daniel Gro{\ss}e and S\"oren Tempel and Rolf Drechsler},
title = {Adaptive Simulation with Virtual Prototypes in an Open-Source {RISC-V} Evaluation Platform},
journal = {Journal of Systems Architecture - Embedded Software Design},
volume = {116},
pages = {102135},
year = {2021},
doi = {10.1016/j.sysarc.2021.102135}
}
@article{USGD:2020,
author = {Buse Ustaoglu and Kenneth Schmitz and Daniel Gro{\ss}e and Rolf Drechsler},
title = {{ReCoFused} partial reconfiguration for secure moving-target countermeasures on {FPGAs}},
journal = {SN Applied Sciences},
volume = {2},
number = {8},
pages = {1--17},
year = {2020},
doi = {10.1007/s42452-020-3003-x}
}
@article{TSF+:2020,
author = {Frank Sill Torres and Pedro Arthur Silva and Geraldo Fontes and Marcel Walter and Jos{\'{e}} Augusto Miranda Nacif and Ricardo Santos Ferreira and Omar Paranaiba Vilela Neto and Jeferson F. Chaves and Robert Wille and Philipp Niemann and Daniel Gro{\ss}e and Rolf Drechsler},
title = {On the impact of the synchronization constraint and interconnections in quantum-dot cellular automata},
journal = {Microprocessors and Microsystems },
volume = {76},
pages = {103109},
year = {2020},
doi = {10.1016/j.micpro.2020.103109}
}
@article{HGPD:2020,
author = {Vladimir Herdt and Daniel Gro{\ss}e and Pascal Pieper and Rolf Drechsler},
title = {{RISC-V} based Virtual Prototype: An Extensible and Configurable Platform for the System-level},
journal = {Journal of Systems Architecture - Embedded Software Design},
year = {2020},
volume = {109},
pages = {101756},
doi = {10.1016/j.sysarc.2020.101756}
}
@article{WWG+:2019,
author = {Marcel Walter and Robert Wille and Daniel Gro{\ss}e and Frank Sill Torres and Rolf Drechsler},
title = {Placement and Routing for Tile-based Field-coupled Nanocomputing Circuits is {NP}-complete},
journal = {Journal on Emerging Technologies in Computing Systems},
volume = {15},
number = {3},
pages = {29:1--29:10},
year = {2019},
doi = {10.1145/3312661}
}
@article{HLGD:2019c,
author = {Vladimir Herdt and Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Combining Sequentialization-based Verification of Multi-Threaded {C} Programs with Symbolic Partial Order Reduction},
journal = {Software Tools for Technology Transfer},
volume = {21},
number = {5},
pages = {545--565},
year = {2019},
doi = {10.1007/s10009-019-00507-5}
}
@article{GHGD:2019,
author = {Mehran Goli and Muhammad Hassan and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Security Validation of {VP}-based {SoCs} Using Dynamic Information Flow Tracking},
journal = {it-Information Technology},
volume = {61},
number = {1},
pages = {45--58},
year = 2019,
doi = {10.1515/itit-2018-0027}
}
@article{HLGD:2018e,
author = {Vladimir Herdt and Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Verifying {SystemC} using Intermediate Verification Language and Stateful Symbolic Simulation},
journal = {IEEE Transactions on Computer Aided Design of Circuits and Systems},
volume = {38},
number = {7},
pages = {1359--1372},
month = {July},
year = 2019,
doi = {10.1109/tcad.2018.2846638}
}
@article{DKS+:2018,
author = {Melanie Diepenbeck and Ulrich K\"uhne and Mathias Soeken and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Behaviour Driven Development for Hardware Design},
journal = {{IPSJ} Trans. System {LSI} Design Methodology},
volume = {11},
pages = {29--45},
year = {2018},
doi = {10.2197/ipsjtsldm.11.29}
}
@article{RHF+:2017,
author = {Heinz Riener and Finn Haedicke and Stefan Frehse and Mathias Soeken and Daniel Gro{\ss}e and Rolf Drechsler and G\"orschwin Fey},
title = {{metaSMT}: Focus on Your Application not on Solver Integration},
journal = {Software Tools for Technology Transfer},
year = {2017},
month = oct,
volume = {19},
number = {5},
pages = {605--621},
doi = {10.1007/s10009-016-0426-1}
}
@article{GFD:2013,
author = {Daniel Gro{\ss}e and G\"orschwin Fey and Rolf Drechsler},
title = {Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis},
journal = {Electronic Communication of the European Association of Software Science and Technology},
volume = {62},
year = {2013},
doi = {10.14279/tuj.eceasst.62.860}
}
@article{LGD:2012b,
author = {Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Automatic {TLM} Fault Localization for {SystemC}},
journal = {IEEE Transactions on Computer Aided Design of Circuits and Systems},
year = 2012,
volume = {31},
number = {8},
month = aug,
pages = {1249--1262},
doi = {10.1109/TCAD.2012.2188800}
}
@article{WGMD:2012,
author = {Robert Wille and Daniel Gro{\ss}e and D. Michael Miller and Rolf Drechsler},
title = {Equivalence Checking of Reversible Circuits},
journal = {Multiple-Valued Logic and Soft Computing},
volume = {19},
number = {4},
year = {2012},
pages = {361--378},
doi = {10.1109/ISMVL.2009.19}
}
@article{WGF+:2011,
author = {Robert Wille and Daniel Gro{\ss}e and Stefan Frehse and Gerhard W. Dueck and Rolf Drechsler},
title = {Debugging Reversible Circuits},
journal = {Integration, the VLSI Journal},
year = 2011,
month = jan,
pages = {51--61},
volume = {44},
number = {1},
doi = {10.1016/j.vlsi.2010.08.002}
}
@article{KGD:2010,
author = {Ulrich K\"uhne and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Towards Fully Automatic Synthesis of Embedded Software},
journal = {IEEE Embedded Systems Letters},
year = {2010},
month = sep,
volume = {2},
number = {3},
pages = {53--57},
doi = {10.1109/LES.2010.2049983}
}
@article{GWDD:2009,
author = {Daniel Gro{\ss}e and Robert Wille and Gerhard W. Dueck and Rolf Drechsler},
title = {Exact Multiple Control {T}offoli Network Synthesis with {SAT} Techniques},
journal = {IEEE Transactions on Computer Aided Design of Circuits and Systems},
volume = {28},
number = {5},
pages = {703--715},
year = 2009,
doi = {10.1109/tcad.2009.2017215}
}
@article{GWDD:2009b,
author = {Daniel Gro{\ss}e and Robert Wille and Gerhard W. Dueck and Rolf Drechsler},
title = {Exact Synthesis of Elementary Quantum Gate Circuits},
journal = {Multiple-Valued Logic and Soft Computing},
volume = {15},
number = {4},
pages = {283--300},
year = 2009,
doi = {10.1109/ISMVL.2008.42}
}
@article{SLR+:2009,
author = {Scholz-Reiter, Bernd and L{\"u}tjen, Michael and Ruthenbeck, Carmen and Harjes, Florian and Drechsler, Rolf and Gro{\ss}e, Daniel},
title = {{Formale Verifikation von logistischen Prozessmodellen}},
journal = {ERP Management},
year = {2009},
volume = {5},
number = {4},
pages = {44-47}
}
@article{GKD:2008,
author = {Daniel Gro{\ss}e and Ulrich K\"uhne and Rolf Drechsler},
title = {Analyzing Functional Coverage in Bounded Model Checking},
journal = {IEEE Transactions on Computer Aided Design of Circuits and Systems},
volume = {27},
number = {7},
month = jul,
pages = {1305--1314},
year = 2008,
doi = {10.1109/tcad.2008.925790}
}
@article{GD:2007,
author = {Daniel Gro{\ss}e and Rolf Drechsler},
title = {{BDD}-Based Verification of Scalable Designs},
journal = {Facta Universitatis. Series: Electronics and Energetics},
volume = {20},
number = 3,
pages = {367--379},
year = {2007},
doi = {10.1109/hldvt.2003.1252485}
}
@article{DG:2005,
author = {Rolf Drechsler and Daniel Gro{\ss}e},
title = {System Level Validation Using Formal Techniques},
journal = {IEE Proceedings Computer \& Digital Techniques, Special Issue on Embedded Microelectronic Systems: Status and Trends},
pages = {393--406},
year = 2005,
volume = 152,
number = 3,
month = may
}
@article{GD:2003b,
author = {Daniel Gro{\ss}e and Rolf Drechsler},
title = {{Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC}},
journal = {it+ti},
year = 2003,
volume = {4},
pages = {219--226},
public = {no},
doi = {10.1524/itit.45.4.219.22731}
}
@article{SDGD:2002,
author = {Frank Schmiedle and Nicole Drechsler and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Heuristic Learning based on Genetic Programming},
journal = {Genetic Programming and Evolvable Machines},
year = 2002,
volume = {3},
pages = {363--388},
public = {no},
doi = {10.1007/3-540-45355-5_1}
}
@inproceedings{SG:2025,
author = {Manfred Schl{\"{a}}gl and Daniel Gro{\ss}e},
title = {Fast Interpreter-Based Instruction Set Simulation for Virtual Prototypes},
booktitle = {Design, Automation and Test in Europe},
year = 2025,
code = {https://github.com/ics-jku/riscv-vp-plusplus},
url = {https://ics.jku.at/files/2025DATE_Fast_Interpreter-based_ISS.pdf}
}
@inproceedings{SG:2024b,
author = {Manfred Schl{\"{a}}gl and Daniel Gro{\ss}e},
title = {Single Instruction Isolation for {RISC-V} Vector Test Failures},
booktitle = {International Conference on Computer-Aided Design},
year = {2024},
code = {https://github.com/ics-jku/RVVTS},
url = {https://ics.jku.at/files/2024ICCAD_Single-Instruction-Isolation-for-RISC-V-Vector-Test-Failures.pdf}
}
@inproceedings{KG:2024d,
title = {An Extensible and Flexible Methodology for Analyzing the Cache Performance of Hardware Designs},
author = {Lucas Klemmer and Daniel Gro{\ss}e},
booktitle = {Forum on Specification and Design Languages},
pages = {1--8},
year = {2024},
url = {https://ics.jku.at/files/2024FDL_WAL-Cache-Performance-Analysis.pdf},
doi = {10.1109/FDL63219.2024.10673859}
}
@inproceedings{KSGG:2024,
author = {Lucas Klemmer and Frans Skarman and Oscar Gustafsson and Daniel Gro{\ss}e},
title = {{Surfer:} A Waveform Viewer as Dynamic as {RISC-V}},
booktitle = {RISC-V Summit Europe},
year = 2024,
code = {https://gitlab.com/surfer-project/surfer},
website = {https://surfer-project.org/},
url = {https://ics.jku.at/files/2024RISCVSummit_Surfer.pdf}
}
@inproceedings{SG:2024,
author = {Manfred Schl{\"{a}}gl and Daniel Gro{\ss}e},
title = {Bounded Load/Stores in Grammar-based Code Generation for Testing the {RISC-V} Vector Extension},
booktitle = {RISC-V Summit Europe},
year = 2024,
code = {https://github.com/ics-jku/RVVTS},
url = {https://ics.jku.at/files/2024RISCVSummit_BoundedLoadStoreGrammarTestRVV.pdf}
}
@inproceedings{HG:2024,
author = {Christoph Hazott and Daniel Gro{\ss}e},
title = {Relation Coverage: A new Paradigm for Hardware/Software Testing},
booktitle = {European Test Symposium},
pages = {1--4},
year = 2024,
url = {https://ics.jku.at/files/2024ETS_relation-coverage.pdf},
code = {https://github.com/ics-jku/relation_coverage},
doi = {10.1109/ETS61313.2024.10567598}
}
@inproceedings{SSG:2024,
author = {Manfred Schl{\"{a}}gl and Moritz Stockinger and Daniel Gro{\ss}e},
title = {A {RISC-V ``V'' VP}: Unlocking Vector Processing for Evaluation at the System Level},
booktitle = {Design, Automation and Test in Europe},
pages = {1--6},
year = 2024,
url = {https://ics.jku.at/files/2024DATE_RISCV-VP-plusplus_RVV.pdf},
code = {https://github.com/ics-jku/riscv-vp-plusplus},
doi = {10.23919/DATE58400.2024.10546838}
}
@inproceedings{GKB:2024,
author = {Daniel Gro{\ss}e and Lucas Klemmer and Dominik Bonora},
title = {Using Formal Verification Methods for Optimization of Circuits under External Constraints},
booktitle = {Design, Automation and Test in Europe},
pages = {1--6},
year = 2024,
url = {https://ics.jku.at/files/2024DATE_FSYN.pdf},
doi = {10.23919/DATE58400.2024.10546556}
}
@inproceedings{HSG:2024,
author = {Christoph Hazott and Florian St\"ogm\"uller and Daniel Gro{\ss}e},
title = {Verifying Embedded Graphics Libraries leveraging Virtual Prototypes and Metamorphic Testing},
booktitle = {ASP Design Automation Conf.},
pages = {275--281},
year = 2024,
url = {https://ics.jku.at/files/2024ASPDAC_Verifying_Embedded_Graphics_Libraries_leveraging_VPs_and_MT.pdf},
code = {https://github.com/ics-jku/mt-graphlib-framework},
doi = {10.1109/ASP-DAC58780.2024.10473799}
}
@inproceedings{KG:2024,
author = {Lucas Klemmer and Daniel Gro{\ss}e},
title = {Towards a Highly Interactive Design-Debug-Verification Cycle},
booktitle = {ASP Design Automation Conf.},
pages = {692--697},
year = 2024,
url = {https://ics.jku.at/files/2024ASPDAC_WAL-VirtualSignals.pdf},
doi = {10.1109/ASP-DAC58780.2024.10473953}
}
@inproceedings{HG:2023,
author = {Christoph Hazott and Daniel Gro{\ss}e},
title = {{DSA} Monitoring Framework for {HW/SW} Partitioning of Application Kernels leveraging {VPs}},
booktitle = {IEEE Design and Verification Conference and Exhibition Europe},
pages = {34--41},
year = 2023,
url = {https://ics.jku.at/files/2023DVConEurope_DSA-Monitoring-Framework-for-HWSW-Partitioning-of-Application-Kernels-leveraging-VPs.pdf}
}
@inproceedings{KBG:2023,
author = {Lucas Klemmer and Dominik Bonora and Daniel Gro{\ss}e},
title = {Large-scale Gatelevel Optimization Leveraging Property Checking},
booktitle = {IEEE Design and Verification Conference and Exhibition Europe},
pages = {86--93},
year = 2023,
url = {https://ics.jku.at/files/2023DVConEurope_PSYN.pdf}
}
@inproceedings{SKGG:2023,
title = {Enhancing Compiler-Driven {HDL} Design with Automatic Waveform Analysis},
author = {Frans Skarman and Lucas Klemmer and Oscar Gustafsson and Daniel Gro{\ss}e},
booktitle = {Forum on Specification and Design Languages},
pages = {1--8},
year = {2023},
url = {https://ics.jku.at/files/2023FDL_Enhancing-Compiler-Driven-HDL-Design-with-WAL.pdf},
doi = {10.1109/FDL59689.2023.10272204}
}
@inproceedings{KG:2023b,
author = {Lucas Klemmer and Daniel Gro{\ss}e},
title = {A {DSL} for Visualizing Pipelines: A {RISC-V} Case Study},
booktitle = {RISC-V Summit Europe},
year = 2023,
url = {https://ics.jku.at/files/2023RISCVSummit_DSLforVisualizingPipelines.pdf}
}
@inproceedings{SG:2023,
author = {Manfred Schl{\"{a}}gl and Daniel Gro{\ss}e},
title = {{GUI-VP Kit}: A {RISC-V} {VP} Meets {Linux} Graphics - Enabling Interactive Graphical Application Development},
booktitle = {ACM Great Lakes Symposium on VLSI},
pages = {599--605},
year = 2023,
url = {https://ics.jku.at/files/2023GLSVLSI_GUI-VP_Kit.pdf},
code = {https://github.com/ics-jku/GUI-VP_Kit},
doi = {10.1145/3583781.3590253}
}
@inproceedings{RG:2023,
author = {Katharina Ruep and Daniel Gro{\ss}e},
title = {Improving Design Understanding of Processors leveraging Datapath Clustering},
booktitle = {Design, Automation and Test in Europe},
pages = {1--2},
year = 2023,
url = {https://ics.jku.at/files/2023DATE_Improving-Design-Understanding-of-Processors-leveraging-Datapath-Clustering.pdf},
doi = {10.23919/DATE56975.2023.10137027}
}
@inproceedings{KJG:2022,
author = {Lucas Klemmer and Eyck Jentzsch and Daniel Gro{\ss}e},
title = {Programmable Analysis of {RISC-V} Processor Simulations using {WAL}},
booktitle = {Design and Verification Conference and Exhibition Europe},
year = 2022,
url = {https://ics.jku.at/files/2022DVCon_Programmable_Analysis_of_RISC-V_Processor_Simulations_using_WAL.pdf}
}
@inproceedings{HVE+:2022b,
author = {Muhammad Hassan and Thilo V\"ortler and Karsten Einwich and Rolf Drechsler and Daniel Gro{\ss}e},
title = {A Cross-domain Heterogeneous {ABV}-Library for Mixed-signal Virtual Prototypes in {SystemC/AMS}},
booktitle = {Design and Verification Conference and Exhibition Europe},
year = 2022,
url = {https://ics.jku.at/files/2022DVCon_Heterogeneous-ABV-Library_SystemC.pdf}
}
@inproceedings{KGG:2022,
title = {Formal Verification of {SUBLEQ} Microcode implementing the {RV32I} {ISA}},
author = {Lucas Klemmer and Sonja Gurtner and Daniel Gro{\ss}e},
booktitle = {Forum on Specification and Design Languages},
pages = {1--8},
year = {2022},
url = {https://ics.jku.at/files/2022FDL_FormalVerificationSUBLEQMicrocode.pdf},
code = {https://github.com/ics-jku/goldcrest-microcode-verification},
note = {{\bf (Best Paper Award)}},
doi = {10.1109/FDL56239.2022.9925662}
}
@inproceedings{KSM+:2022,
author = {Alexander Konrad and Christoph Scholl and Alireza Mahzoon and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Divider Verification Using Symbolic Computer Algebra and Delayed Don't Care Optimization},
booktitle = {Int'l Conf. on Formal Methods in CAD},
pages = {108--117},
year = {2022},
url = {https://ics.jku.at/files/2022FMCAD_Divider-Verification-using-SCA-and-DDCO.pdf},
doi = {10.34727/2022/isbn.978-3-85448-053-2_17}
}
@inproceedings{KG:2022d,
author = {Lucas Klemmer and Daniel Gro{\ss}e},
title = {An Exploration Platform for Microcoded {RISC-V} Cores Leveraging the One Instruction Set Computer Principle},
booktitle = {IEEE Annual Symposium on VLSI},
pages = {38--43},
year = 2022,
url = {https://ics.jku.at/files/2022ISVLSI_ExplorationPlatform_RISC-V_OISC.pdf},
code = {https://github.com/ics-jku/goldcrest-vp},
doi = {10.1109/ISVLSI54635.2022.00020}
}
@inproceedings{KSG:2022,
author = {Lucas Klemmer and Manfred Schl{\"{a}}gl and Daniel Gro{\ss}e},
title = {{RVVRadar:} A Framework for Supporting the Programmer in Vectorization for {RISC-V}},
booktitle = {ACM Great Lakes Symposium on VLSI},
pages = {183--187},
year = 2022,
url = {https://ics.jku.at/files/2022GLSVLSI_RVVRadar.pdf},
code = {https://github.com/ics-jku/RVVRadar},
doi = {10.1145/3526241.3530388}
}
@inproceedings{BHGD:2022,
author = {Niklas Bruns and Vladimir Herdt and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing},
booktitle = {ACM Great Lakes Symposium on VLSI},
pages = {97--103},
year = 2022,
url = {https://ics.jku.at/files/2022GLSVLSI_Crosslevel-Processor-Verification-using-CGF.pdf},
doi = {10.1145/3526241.3530340}
}
@inproceedings{KG:2022c,
author = {Lucas Klemmer and Daniel Gro{\ss}e},
title = {Waveform-based performance analysis of {RISC-V} processors: late breaking results},
booktitle = {Design Automation Conf.},
pages = {1404--1405},
year = 2022,
url = {https://ics.jku.at/files/2022DAC_LBR-Waveform-based-Performance-Analyisis-for-RISC-V.pdf},
doi = {10.1145/3489517.3530623}
}
@inproceedings{MGS+:2022,
author = {Alireza Mahzoon and Daniel Gro{\ss}e and Christoph Scholl and Alexander Konrad and Rolf Drechsler},
title = {Formal Verification of Modular Multipliers using Symbolic Computer Algebra and Boolean Satisfiability},
booktitle = {Design Automation Conf.},
pages = {1183--1188},
year = {2022},
url = {https://ics.jku.at/files/2022DAC_Formal-Verification-of-Modular-Multipliers-using-SCA-and-SAT.pdf},
doi = {10.1145/3489517.3530605}
}
@inproceedings{PHGD:2022,
title = {Verifying {SystemC} {TLM} Peripherals using Modern {C++} Symbolic Execution Tools},
author = {Pascal Pieper and Vladimir Herdt and Daniel Gro{\ss}e and Rolf Drechsler},
booktitle = {Design Automation Conf.},
pages = {1177--1182},
year = {2022},
url = {https://ics.jku.at/files/2022DAC_Verifying-SystemC-TLM-Peripherals-using-SymEx.pdf},
doi = {10.1145/3489517.3530604}
}
@inproceedings{RG:2022,
author = {Katharina Ruep and Daniel Gro{\ss}e},
title = {{SpinalFuzz}: Coverage-Guided Fuzzing for {SpinalHDL} Designs},
booktitle = {European Test Symposium},
pages = {1--4},
year = 2022,
url = {https://ics.jku.at/files/2022ETS_SpinalFuzz.pdf},
code = {https://github.com/ics-jku/spinalfuzz},
doi = {10.1109/ETS54262.2022.9810421}
}
@inproceedings{KG:2022,
author = {Lucas Klemmer and Daniel Gro{\ss}e},
title = {{WAL:} A Novel Waveform Analysis Language for Advanced Design Understanding and Debugging},
booktitle = {ASP Design Automation Conf.},
pages = {358--364},
year = 2022,
website = {https://wal-lang.org},
pdf = {https://ics.jku.at/files/2022ASPDAC_WAL.pdf},
code = {https://github.com/ics-jku/wal},
doi = {10.1109/ASP-DAC52403.2022.9712600}
}
@inproceedings{RHGD:2021,
author = {Frank Riese and Vladimir Herdt and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Metamorphic Testing for Processor Verification: A {RISC-V} Case Study at the Instruction Level},
booktitle = {VLSI of System-on-Chip},
pages = {1--6},
year = 2021,
url = {https://ics.jku.at/files/2021VLSI-SoC_Metamorphic-Testing-for-Processor-Verification.pdf},
doi = {10.1109/VLSI-SoC53125.2021.9606997}
}
@inproceedings{KG:2021,
author = {Lucas Klemmer and Daniel Gro{\ss}e},
title = {{EPEX:} Processor Verification by Equivalent Program Execution},
booktitle = {ACM Great Lakes Symposium on VLSI},
pages = {33--38},
year = 2021,
url = {https://ics.jku.at/files/2021GLSVLSI_EPEX.pdf},
doi = {10.1145/3453688.3461497}
}
@inproceedings{KFDG:2021,
author = {Lucas Klemmer and Saman Froehlich and Rolf Drechsler and Daniel Gro{\ss}e},
title = {{XbNN}: Enabling {CNNs} on Edge Devices by Approximate On-Chip Dot Product Encoding},
booktitle = {IEEE International Symposium on Circuits and Systems},
pages = {1--5},
year = 2021,
url = {https://ics.jku.at/files/2021ISCAS_XbNN.pdf},
doi = {10.1109/ISCAS51556.2021.9401780}
}
@inproceedings{SKM+:2021,
author = {Christoph Scholl and Alexander Konrad and Alireza Mahzoon and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Verifying Dividers Using Symbolic Computer Algebra and Don't Care Optimization},
booktitle = {Design, Automation and Test in Europe},
pages = {1110--1115},
year = {2021},
url = {https://ics.jku.at/files/2021DATE_Verifying-dividers-using-SCA-and-DC-optimization.pdf},
doi = {10.23919/DATE51398.2021.9474019}
}
@inproceedings{HGD:2021b,
title = {System Level verification of Phase-Locked Loop using Metamorphic Relations},
author = {Muhammad Hassan and Daniel Gro{\ss}e and Rolf Drechsler},
booktitle = {Design, Automation and Test in Europe},
pages = {1378--1381},
year = {2021},
url = {https://ics.jku.at/files/2021DATE_SystemLevel-PLL-Metamorphic.pdf},
note = {{\bf (Best Paper Candidate)}},
doi = {10.23919/DATE51398.2021.9474211}
}
@inproceedings{HGD:2021,
title = {System-Level Verification of Linear and Non-Linear Behaviors of {RF} Amplifiers using Metamorphic Relations},
author = {Muhammad Hassan and Daniel Gro{\ss}e and Rolf Drechsler},
booktitle = {ASP Design Automation Conf.},
pages = {761--766},
year = {2021},
url = {https://ics.jku.at/files/2021ASPDAC_RF_Metamorphic.pdf},
doi = {10.1145/3394885.3431592}
}
@inproceedings{HTGD:2021,
title = {Mutation-based Compliance Testing for {RISC-V}},
author = {Vladimir Herdt and S\"oren Tempel and Daniel Gro{\ss}e and Rolf Drechsler},
booktitle = {ASP Design Automation Conf.},
pages = {55--60},
year = {2021},
url = {https://ics.jku.at/files/2021ASPDAC_Mutation_based_Compliance_Testing.pdf},
doi = {10.1145/3394885.3431584}
}
@inproceedings{HGTD:2020,
title = {Adaptive Simulation with Virtual Prototypes for {RISC-V}: Switching Between Fast and Accurate at Runtime},
author = {Vladimir Herdt and Daniel Gro{\ss}e and S\"oren Tempel and Rolf Drechsler},
booktitle = {Int'l Conf. on Comp. Design},
pages = {312--315},
year = {2020},
url = {https://ics.jku.at/files/2020ICCD_vp_based_adaptive_simulation.pdf},
doi = {10.1109/ICCD50377.2020.00059}
}
@inproceedings{MWGD:2020,
author = {Tim Meywerk and Marcel Walter and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Clustering-Guided {SMT(LRA)} Learning},
booktitle = {International Conference on integrated Formal Methods},
pages = {41--59},
year = {2020},
url = {https://ics.jku.at/files/2020iFM_SMTLearning.pdf},
doi = {10.1007/978-3-030-63461-2_3}
}
@inproceedings{MWH+:2020,
author = {Tim Meywerk and Marcel Walter and Vladimir Herdt and Jan Kleinekath\"ofer and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Verifying Safety Properties of Robotic Plans operating in Real-World Environments via Logic-based Environment Modeling},
booktitle = {International Symposium On Leveraging Applications of Formal Methods, Verification and Validation},
pages = {326--347},
year = {2020},
url = {https://ics.jku.at/files/2020ISoLA_VerifyingSafetyProperties_DEC.pdf},
doi = {10.1007/978-3-030-61467-6_21}
}
@inproceedings{HGJD:2020,
title = {Efficient Cross-Level Testing for Processor Verification: A {RISC-V} Case-Study},
author = {Vladimir Herdt and Daniel Gro{\ss}e and Eyck Jentzsch and Rolf Drechsler},
booktitle = {Forum on Specification and Design Languages},
year = {2020},
pages = {1--7},
url = {https://ics.jku.at/files/2020FDL_cross-level-processor-verification-riscv.pdf},
note = {{\bf (Best Paper Award)}},
doi = {10.1109/FDL50818.2020.9232941}
}
@inproceedings{HGD:2020d,
author = {Vladimir Herdt and Daniel Gro{\ss}e and Rolf Drechsler},
title = {{RVX} - A Tool for Concolic Testing of Embedded Binaries Targeting {RISC-V} Platforms},
booktitle = {Automated Technology for Verification and Analysis},
pages = {543--549},
year = {2020},
url = {https://ics.jku.at/files/2020ATVA_RVX.pdf},
doi = {10.1007/978-3-030-59152-6_31}
}
@inproceedings{LGGD:2020,
author = {David Lemma and Mehran Goli and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Towards Generation of a Programmable Power Management Unit at the Electronic System Level},
booktitle = {IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems},
pages = {1--6},
year = 2020,
doi = {10.1109/DDECS50862.2020.9095712}
}
@inproceedings{BGD:2020,
author = {Niklas Bruns and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Early Verification of {ISA} Extension Specifications Using Deep Reinforcement Learning},
booktitle = {ACM Great Lakes Symposium on VLSI},
pages = {297--302},
year = {2020},
url = {https://ics.jku.at/files/2020GLSVLSI_Early-Verification-of-ISA-Extension-Specifications-using-Deep-Reinforcment-Learning.pdf},
doi = {10.1145/3386263.3406901}
}
@inproceedings{HGW+:2020,
author = {Vladimir Herdt and Daniel Gro{\ss}e and Jonas Wloka and Tim G{\"u}neysu and Rolf Drechsler},
title = {Verification of Embedded Binaries using Coverage-guided Fuzzing with {SystemC}-based Virtual Prototypes},
booktitle = {ACM Great Lakes Symposium on VLSI},
pages = {101--106},
year = {2020},
url = {https://ics.jku.at/files/2020GLSVLSI_Verification-of-Embedded-Binaries-using-Coverage-guided-Fuzzing-with-SystemC-Virtual-Prototypes.pdf},
doi = {10.1145/3386263.3406899}
}
@inproceedings{HGD:2020c,
title = {Closing the {RISC-V} Compliance Gap: Looking from the Negative Testing Side},
author = {Vladimir Herdt and Daniel Gro{\ss}e and Rolf Drechsler},
booktitle = {Design Automation Conf.},
pages = {1--6},
year = {2020},
url = {https://ics.jku.at/files/2020DAC_ClosingtheRISC-VComplianceGap-LookingfromtheNegativeTestingSide.pdf},
doi = {10.1109/DAC18072.2020.9218629}
}
@inproceedings{PHGD:2020,
title = {Dynamic Information Flow Tracking for Embedded Binaries using {SystemC-based} Virtual Prototypes},
author = {Pascal Pieper and Vladimir Herdt and Daniel Gro{\ss}e and Rolf Drechsler},
booktitle = {Design Automation Conf.},
pages = {1--6},
year = {2020},
url = {https://ics.jku.at/files/2020DAC_DynamicInformationFlowTrackingforEmbeddedBinariesusingSystemC-basedVPs.pdf},
doi = {10.1109/DAC18072.2020.9218494}
}
@inproceedings{WWT+:2020,
title = {Verification for Field-coupled Nanocomputing Circuits},
author = {Marcel Walter and Robert Wille and Frank Sill Torres and Daniel Gro{\ss}e and Rolf Drechsler},
booktitle = {Design Automation Conf.},
pages = {1--6},
year = {2020},
url = {https://ics.jku.at/files/2020DAC_Verification_for_Field-coupled_Nanocomputing_Circuits.pdf},
doi = {10.1109/DAC18072.2020.9218641}
}
@inproceedings{FKGD:2020,
author = {Saman Froehlich and Lucas Klemmer and Daniel Gro{\ss}e and Rolf Drechsler},
title = {{ASNet}: Introducing Approximate Hardware to High-Level Synthesis of Neural Networks},
booktitle = {International Symposium on {M}ulti-{V}alued {L}ogic},
pages = {64--69},
year = {2020},
url = {https://ics.jku.at/files/2020ISMVL_ASNet.pdf},
doi = {10.1109/ISMVL49045.2020.00-28}
}
@inproceedings{MGSD:2020,
author = {Alireza Mahzoon and Daniel Gro{\ss}e and Christoph Scholl and Rolf Drechsler},
title = {Towards Formal Verification of Optimized and Industrial Multipliers},
booktitle = {Design, Automation and Test in Europe},
pages = {544--549},
year = {2020},
url = {https://ics.jku.at/files/2020DATE_Towards_formal_verification_of_optimized_and_industrial_multipliers.pdf},
doi = {10.23919/DATE48585.2020.9116485}
}
@inproceedings{HGD:2020,
author = {Vladimir Herdt and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Fast and Accurate Performance Evaluation for {RISC-V} using Virtual Prototypes},
booktitle = {Design, Automation and Test in Europe},
pages = {618--621},
year = {2020},
url = {https://ics.jku.at/files/2020DATE_Fast_and_Accurate_Performance_Evaluation_RISC-V_VPs.pdf},
doi = {10.23919/DATE48585.2020.9116522}
}
@inproceedings{HGD:2020b,
author = {Vladimir Herdt and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Towards Specification and Testing of {RISC-V} {ISA} Compliance},
booktitle = {Design, Automation and Test in Europe},
pages = {995--998},
year = {2020},
url = {https://ics.jku.at/files/2020DATE_Towards_Specification_and_Testing_of_RISC-V_Compliance.pdf},
doi = {10.23919/DATE48585.2020.9116193}
}
@inproceedings{DG:2019,
author = {Rolf Drechsler and Daniel Gro{\ss}e},
title = {Ensuring Correctness of Next Generation Devices: From Reconfigurable to Self-Learning Systems},
booktitle = {Asian Test Symp.},
pages = {159--164},
year = {2019},
url = {https://ics.jku.at/files/2019ATS_EnsuringCorrectnessofNextGenerationDevices.pdf},
doi = {10.1109/ATS47505.2019.00029}
}
@inproceedings{HGV+:2019,
author = {Muhammad Hassan and Daniel Gro{\ss}e and Thilo V\"ortler and Karsten Einwich and Rolf Drechsler},
title = {Functional Coverage-Driven Characterization of {RF} Amplifiers},
booktitle = {Forum on Specification and Design Languages},
year = {2019},
url = {https://ics.jku.at/files/2019FDL_FunctionalCoverage-DrivenCharacterizationOfRFAmplifiers.pdf},
pages = {1-8},
note = {{\bf (Best Paper Candidate)}},
doi = {10.1109/fdl.2019.8876957}
}
@inproceedings{HGD+:2019,
title = {Systematic {RISC-V} based Firmware Design},
author = {Vladimir Herdt and Daniel Gro{\ss}e and Rolf Drechsler and Christoph Gerum and Alexander Jung and Joscha-Joel Benz and Oliver Bringmann and Michael Schwarz and Dominik Stoffel and Wolfgang Kunz},
booktitle = {Forum on Specification and Design Languages},
pages = {1-8},
year = {2019},
url = {https://ics.jku.at/files/2019FDL_Systematic_RISC-V_based_FW-Design.pdf},
doi = {10.1109/fdl.2019.8876945}
}
@inproceedings{MWH+:2019,
author = {Tim Meywerk and Marcel Walter and Vladimir Herdt and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Towards Formal Verification of Plans for Cognition-enabled Autonomous Robotic Agents},
booktitle = {EUROMICRO Symposium on Digital System Design},
pages = {129--136},
year = {2019},
url = {https://ics.jku.at/files/2019DSD_TowardsFormalPlanVerification.pdf},
doi = {10.1109/dsd.2019.00029}
}
@inproceedings{UHT+:2019,
author = {Buse Ustaoglu and Sebastian Huhn and Frank Sill Torres and Daniel Gro{\ss}e and Rolf Drechsler},
title = {{SAT-Hard}: A Learning-based Hardware {SAT}-Solver},
booktitle = {EUROMICRO Symposium on Digital System Design},
pages = {74--81},
year = {2019},
url = {https://ics.jku.at/files/2019_DSD_HW-SAT-Solver_with_Learning.pdf},
doi = {10.1109/dsd.2019.00021}
}
@inproceedings{WWT+:2019b,
author = {Robert Wille and Marcel Walter and Frank Sill Torres and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Ignore Clocking Constraints: An Alternative Physical Design Methodology for Field-coupled Nanotechnologies},
booktitle = {IEEE Annual Symposium on VLSI},
pages = {651--656},
year = {2019},
url = {https://ics.jku.at/files/2019_ISVLSI_Ignore_Clocking_Constraints_An_Alternative_Physical_Design_Methodology_for_Field-coupled_Nanotechnologies.pdf},
doi = {10.1109/isvlsi.2019.00121}
}
@inproceedings{GHGD:2019b,
author = {Mehran Goli and Muhammad Hassan and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Automated Analysis of Virtual Prototypes at Electronic System Level},
booktitle = {ACM Great Lakes Symposium on VLSI},
pages = {307--310},
year = {2019},
url = {https://ics.jku.at/files/2019GLSVLSI_VP-Analysis.pdf},
doi = {10.1145/3299874.3318024}
}
@inproceedings{HGLD:2019c,
title = {Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A {RISC-V} Case Study},
author = {Vladimir Herdt and Daniel Gro{\ss}e and Hoang M. Le and Rolf Drechsler},
booktitle = {Design Automation Conf.},
pages = {188:1--188:6},
year = {2019},
url = {https://ics.jku.at/files/2019DAC_Early_Concolic_Testing_of_Embedded_Binaries_with_Virtual_Prototypes.pdf},
doi = {10.1145/3316781.3317807}
}
@inproceedings{MGD:2019,
author = {Alireza Mahzoon and Daniel Gro{\ss}e and Rolf Drechsler},
title = {{RevSCA}: Using Reverse Engineering to Bring Light into Backward Rewriting for Big and Dirty Multipliers},
booktitle = {Design Automation Conf.},
pages = {185:1--185:6},
year = {2019},
url = {https://ics.jku.at/files/2019DAC_RevSCA.pdf},
doi = {10.1145/3316781.3317898}
}
@inproceedings{SUGD:2019,
author = {Kenneth Schmitz and Buse Ustaoglu and Daniel Gro{\ss}e and Rolf Drechsler},
title = {{(ReCo)Fuse} Your {PRC} or Lose Security: Finally Reliable Reconfiguration-based Countermeasures on {FPGAs}},
booktitle = {International Symposium on Applied Reconfigurable Computing},
pages = {112--126},
year = {2019},
url = {https://ics.jku.at/files/2019ARC_ReCoFuse.pdf},
doi = {10.1007/978-3-030-17227-5_9}
}
@inproceedings{LGBD:2019,
author = {Hoang M. Le and Daniel Gro{\ss}e and Niklas Bruns and Rolf Drechsler},
title = {Detection of Hardware Trojans in {SystemC HLS} Designs via Coverage-guided Fuzzing},
booktitle = {Design, Automation and Test in Europe},
pages = {602--605},
year = {2019},
url = {https://ics.jku.at/files/2019DATE_Detection_of_Hardware_Trojans_in_SystemC_HLS_Designs_via_Coverage-guided_Fuzzing.pdf},
doi = {10.23919/date.2019.8714927}
}
@inproceedings{HGLD:2019b,
author = {Muhammad Hassan and Daniel Gro{\ss}e and Hoang M. Le and Rolf Drechsler},
title = {Data Flow Testing for {SystemC-AMS} Timed Data Flow Models},
booktitle = {Design, Automation and Test in Europe},
pages = {366--371},
year = {2019},
url = {https://ics.jku.at/files/2019DATE_Data_Flow_Testing_for_SystemC-AMS_Timed_Data_Flow_Models.pdf},
doi = {10.23919/date.2019.8714903}
}
@inproceedings{HGLD:2019,
title = {Verifying Instruction Set Simulators using Coverage-guided Fuzzing},
author = {Vladimir Herdt and Daniel Gro{\ss}e and Hoang M. Le and Rolf Drechsler},
booktitle = {Design, Automation and Test in Europe},
pages = {360--365},
year = {2019},
url = {https://ics.jku.at/files/2019DATE_Verifying_Instruction_Set_Simulators_using_Coverage-guided_Fuzzing.pdf},
doi = {10.23919/DATE.2019.8714912}
}
@inproceedings{FGD:2019,
author = {Saman Froehlich and Daniel Gro{\ss}e and Rolf Drechsler},
title = {One Method - All Error-Metrics: A Three-Stage Approach for Error-Metric Evaluation in Approximate Computing},
booktitle = {Design, Automation and Test in Europe},
pages = {284--287},
year = {2019},
url = {https://ics.jku.at/files/2019DATE_OneMethod-AllError-Metrics_A_Three-Stage_Approach_for_Error-Metric_Evaluation_in_AC.pdf},
doi = {10.23919/date.2019.8715138}
}
@inproceedings{HLGD:2019,
title = {Maximizing Power State Cross Coverage in Firmware-based Power Management},
author = {Vladimir Herdt and Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler},
booktitle = {ASP Design Automation Conf.},
pages = {335--340},
year = {2019},
url = {https://ics.jku.at/files/2019ASPDAC_MaximizingPowerStateCrossCoverageinFirmware-basedPowerManagement.pdf},
doi = {10.1145/3287624.3287631}
}
@inproceedings{WWT+:2019,
title = {Scalable Design for Field-coupled Nanocomputing Circuits},
author = {Marcel Walter and Robert Wille and Frank Sill Torres and Daniel Gro{\ss}e and Rolf Drechsler},
booktitle = {ASP Design Automation Conf.},
pages = {197--202},
year = {2019},
url = {https://ics.jku.at/files/2019_ASP-DAC_Scalable_Design_for_Field-coupled_Nanocomputing_Circuits.pdf},
doi = {10.1145/3287624.3287705}
}
@inproceedings{LGGD:2018,
author = {David Lemma and Mehran Goli and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Power Intent from Initial {ESL} Prototypes: Extracting Power Management Parameters},
booktitle = {Nordic Circuits and Systems Conference},
pages = {1--6},
year = 2018,
url = {https://ics.jku.at/files/2018NORCAS_ESL_extr_pwr_params.pdf},
doi = {10.1109/norchip.2018.8573511}
}
@inproceedings{VEHG:2018,
author = {Thilo V\"ortler and Karsten Einwich and Muhammad Hassan and Daniel Gro{\ss}e},
title = {Using Constraints for {SystemC} {AMS} Design and Verification},
booktitle = {Design and Verification Conference and Exhibition Europe},
year = {2018},
url = {https://ics.jku.at/files/2018DVConEurope_SystemC-AMS_Constraints.pdf},
note = {{\bf (Best Paper Award)}}
}
@inproceedings{HGLD:2018,
title = {Extensible and Configurable {RISC-V} based Virtual Prototype},
author = {Vladimir Herdt and Daniel Gro{\ss}e and Hoang M. Le and Rolf Drechsler},
booktitle = {Forum on Specification and Design Languages},
pages = {5--16},
year = {2018},
url = {https://ics.jku.at/files/2018FDL_RISCV_VP.pdf},
doi = {10.1109/FDL.2018.8524047}
}
@inproceedings{MGD:2018b,
author = {Alireza Mahzoon and Daniel Gro{\ss}e and Rolf Drechsler},
title = {{PolyCleaner:} Clean your Polynomials before Backward Rewriting to Verify Million-gate Multipliers},
booktitle = {International Conference on Computer-Aided Design},
pages = {129:1--129:8},
year = {2018},
url = {https://ics.jku.at/files/2018ICCAD_PolyCleaner.pdf},
note = {{\bf (Best Paper Award)}},
doi = {10.1145/3240765.3240837}
}
@inproceedings{FGD:2018b,
author = {Saman Froehlich and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Towards Reversed Approximate Hardware Design},
booktitle = {EUROMICRO Symposium on Digital System Design},
pages = {665--671},
year = {2018},
url = {https://ics.jku.at/files/2018DSD_TowardsReversedApproximateHWDesign.pdf},
doi = {10.1109/dsd.2018.00112}
}
@inproceedings{TWW+:2018b,
author = {Frank Sill Torres and Robert Wille and Marcel Walter and Philipp Niemann and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Evaluating the Impact of Interconnections in Quantum-Dot Cellular Automata},
booktitle = {EUROMICRO Symposium on Digital System Design},
pages = {649--656},
year = {2018},
url = {https://ics.jku.at/files/2018DSD_ImpactOfInterconnectionsInQCA.pdf},
doi = {10.1109/dsd.2018.00110}
}
@inproceedings{TWW+:2018,
author = {Frank Sill Torres and Marcel Walter and Robert Wille and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Synchronization of Clocked Field-Coupled Circuits},
booktitle = {International Conference on Nanotechnology},
year = {2018},
url = {https://ics.jku.at/files/2018NANO_SynchronizationOfClockedFieldCoupledCircuits.pdf},
doi = {10.1109/nano.2018.8626294}
}
@inproceedings{MGD:2018,
author = {Alireza Mahzoon and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex Multipliers},
booktitle = {IEEE Annual Symposium on VLSI},
pages = {351--356},
year = {2018},
url = {https://ics.jku.at/files/2018ISVLSI_SCASAT_DebuggingAndFixing.pdf},
doi = {10.1109/isvlsi.2018.00071}
}
@inproceedings{SKS+:2018,
author = {Kenneth Schmitz and Oliver Kesz{\"o}cze and Jurij Schmidt and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Towards Dynamic Execution Environment for System Security Protection against Hardware Flaws},
booktitle = {IEEE Annual Symposium on VLSI},
pages = {557--562},
year = {2018},
url = {https://ics.jku.at/files/2018ISVLSI_DynamicProgramExecution_QEMU.pdf},
doi = {10.1109/isvlsi.2018.00107}
}
@inproceedings{LGD:2018,
author = {David Lemma and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Natural Language based Power Domain Partitioning},
booktitle = {IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems},
pages = {101--106},
year = 2018,
url = {https://ics.jku.at/files/2018DDECS_NLbasedPDP.pdf},
doi = {10.1109/ddecs.2018.00025}
}
@inproceedings{UHGD:2018,
author = {Buse Ustaoglu and Sebastian Huhn and Daniel Gro{\ss}e and Rolf Drechsler},
title = {{SAT-Lancer:} A Hardware {SAT}-Solver for Self-Verification},
booktitle = {ACM Great Lakes Symposium on VLSI},
pages = {479--482},
year = {2018},
url = {https://ics.jku.at/files/2018GLSVLSI_SAT-Lancer.pdf},
doi = {10.1145/3194554.3194643}
}
@inproceedings{HGL+:2018,
author = {Muhammad Hassan and Daniel Gro{\ss}e and Hoang M. Le and Thilo V\"ortler and Karsten Einwich and Rolf Drechsler},
title = {Testbench Qualification for {SystemC-AMS} Timed Data Flow Models},
pages = {857--860},
booktitle = {Design, Automation and Test in Europe},
year = {2018},
url = {https://ics.jku.at/files/2018DATE_TestbenchQualificationForSystemCAMSTDF.pdf},
doi = {10.23919/date.2018.8342125}
}
@inproceedings{FGD:2018,
author = {Saman Froehlich and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Approximate Hardware Generation using Symbolic Computer Algebra employing {Gr\"obner} Basis},
booktitle = {Design, Automation and Test in Europe},
pages = {889--892},
year = {2018},
url = {https://ics.jku.at/files/2018DATE_ApproxHardwareGeneration_SCA.pdf},
doi = {10.23919/date.2018.8342133}
}
@inproceedings{WWG+:2018,
author = {Marcel Walter and Robert Wille and Daniel Gro{\ss}e and Frank Sill Torres and Rolf Drechsler},
title = {An Exact Method for Design Exploration of {Quantum-dot Cellular Automata}},
booktitle = {Design, Automation and Test in Europe},
pages = {503--508},
year = {2018},
url = {https://ics.jku.at/files/2018DATE_ExactMethodforDesignExplorationOfQCA.pdf},
doi = {10.23919/date.2018.8342060}
}
@inproceedings{LHGD:2018,
author = {Hoang M. Le and Vladimir Herdt and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Resiliency Evaluation via Symbolic Fault Injection on Intermediate Code},
booktitle = {Design, Automation and Test in Europe},
pages = {845--850},
year = {2018},
url = {https://ics.jku.at/files/2018DATE_symbolic-swifi-llvm.pdf},
doi = {10.23919/date.2018.8342123}
}
@inproceedings{HLGD:2018,
author = {Vladimir Herdt and Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Towards Fully Automated {TLM-to-RTL} Property Refinement},
booktitle = {Design, Automation and Test in Europe},
pages = {1508--1511},
year = {2018},
url = {https://ics.jku.at/files/2018DATE_TowardsFullyAutomatedTLM-to-RTLPropertyRefinement.pdf},
doi = {10.23919/date.2018.8342253}
}
@inproceedings{CEGD:2018,
author = {Arun Chandrasekharan and Stephan Eggersgl\"u{\ss} and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Approximation-aware Testing for Approximate Circuits},
booktitle = {ASP Design Automation Conf.},
pages = {239--244},
year = {2018},
url = {https://ics.jku.at/files/2018ASPDAC_ApproxAwareTesting.pdf},
doi = {10.1109/aspdac.2018.8297312}
}
@inproceedings{DG:2017,
author = {Rolf Drechsler and Daniel Gro{\ss}e},
title = {Verifying Next Generation Electronic Systems},
booktitle = {International Conference on Infocom Technologies and Unmanned Systems},
pages = {6--10},
year = {2017},
url = {https://ics.jku.at/files/2017ICTUS_VerifyingNextGenerationElectronicSystems.pdf},
doi = {10.1109/ictus.2017.8285965}
}
@inproceedings{CGD:2017b,
author = {Arun Chandrasekharan and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Yise - A novel Framework for Boolean Networks using {Y}-Inverter Graphs},
booktitle = {ACM \& IEEE International Conference on Formal Methods and Models for Codesign},
year = {2017},
url = {https://ics.jku.at/files/2017MEMOCODE_Yise.pdf},
pages = {114-117},
doi = {10.1145/3127041.3127065}
}
@inproceedings{HLGD:2017,
title = {Towards Early Validation of Firmware-Based Power Management using Virtual Prototypes: A Constrained Random Approach},
author = {Vladimir Herdt and Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler},
booktitle = {Forum on Specification and Design Languages},
year = {2017},
url = {https://ics.jku.at/files/2017FDL_early_validation_of_firmware_based_power_management.pdf},
pages = {1-8},
mycomment = {{\bf (Best Paper Candidate)}},
doi = {10.1109/FDL.2017.8303898}
}
@inproceedings{MSGD:2017,
author = {Rehab Massoud and Jannis Stoppe and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Semi-Formal Cycle-Accurate Temporal Execution Traces Reconstruction},
booktitle = {International Conference on Formal Modelling and Analysis of Timed Systems},
year = {2017},
url = {https://ics.jku.at/files/2017FORMATS_Semi-FormalCycle-AccurateTemporalExecutionTracesReconstruction.pdf},
pages = {335--351},
doi = {10.1007/978-3-319-65765-3_19}
}
@inproceedings{HHL+:2017b,
author = {Muhammad Hassan and Vladimir Herdt and Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Early {SoC} Security Validation by {VP}-based Static Information Flow Analysis},
booktitle = {International Conference on Computer-Aided Design},
year = {2017},
url = {https://ics.jku.at/files/2017ICCAD_early_soc_security_validation.pdf},
pages = {400--407},
doi = {10.1109/iccad.2017.8203805}
}
@inproceedings{SSGD:2017,
author = {Saeideh Shirinzadeh and Mathias Soeken and Daniel Gro{\ss}e and Rolf Drechsler},
title = {An Adaptive Prioritized $\epsilon$-Preferred Evolutionary Algorithm for Approximate {BDD} Optimization},
booktitle = {Genetic and Evolutionary Computation Conference},
year = {2017},
url = {https://ics.jku.at/files/2017gecco_AdaptiveEA_ApproxBDD.pdf},
pages = {1232--1239},
doi = {10.1145/3071178.3071281}
}
@inproceedings{CGD:2017,
author = {Arun Chandrasekharan and Daniel Gro{\ss}e and Rolf Drechsler},
title = {{ProACt:} A Processor for High Performance On-demand Approximate Computing},
booktitle = {ACM Great Lakes Symposium on VLSI},
year = {2017},
url = {https://ics.jku.at/files/2017GLSVLSI_ProACt.pdf},
pages = {463--466},
doi = {10.1145/3060403.3060415}
}
@inproceedings{FGD:2017b,
author = {Saman Froehlich and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Error Bounded Exact {BDD} Minimization in Approximate Computing},
booktitle = {International Symposium on {M}ulti-{V}alued {L}ogic},
year = {2017},
url = {https://ics.jku.at/files/2017ISMVL_EBEBM.pdf},
pages = {254--259},
doi = {10.1109/ISMVL.2017.11}
}
@inproceedings{HHL+:2017,
author = {Muhammad Hassan and Vladimir Herdt and Hoang M. Le and Mingsong Chen and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Data Flow Testing for Virtual Prototypes},
booktitle = {Design, Automation and Test in Europe},
year = {2017},
url = {https://ics.jku.at/files/2017DATE_dataflowtesting_for_vps.pdf},
pages = {380--385},
doi = {10.23919/date.2017.7927020}
}
@inproceedings{SCF+:2017,
author = {Kenneth Schmitz and Arun Chandrasekharan and Jonas Gomes Filho and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Trust is good, Control is better: Hardware-based Instruction-Replacement for Reliable Processor-{IPs}},
booktitle = {ASP Design Automation Conf.},
year = {2017},
url = {https://ics.jku.at/files/2017ASPDAC_InstructionReplacement.pdf},
pages = {57--62},
doi = {10.1109/aspdac.2017.7858296}
}
@inproceedings{GLHD:2016,
author = {Daniel Gro{\ss}e and Hoang M. Le and Muhammad Hassan and Rolf Drechsler},
title = {Guided Lightweight Software Test Qualification for {IP} Integration using Virtual Prototypes},
booktitle = {Int'l Conf. on Comp. Design},
year = {2016},
url = {https://ics.jku.at/files/2016ICCD_SWTestQualificationIPVP.pdf},
pages = {606--613},
doi = {10.1109/iccd.2016.7753347}
}
@inproceedings{SGSD:2016,
author = {Amr Sayed-Ahmed and Daniel Gro{\ss}e and Mathias Soeken and Rolf Drechsler},
title = {Equivalence Checking Using {Gr\"obner} Bases},
booktitle = {Int'l Conf. on Formal Methods in CAD},
year = {2016},
url = {https://ics.jku.at/files/2016FMCAD_ACEC.pdf},
pages = {169--176},
doi = {10.1109/fmcad.2016.7886676}
}
@inproceedings{HLGD:2016c,
title = {On the Application of Formal Fault Localization to Automated {RTL-to-TLM} Fault Correspondence Analysis for Fast and Accurate {VP}-based Error Effect Simulation - A Case Study},
author = {Vladimir Herdt and Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler},
booktitle = {Forum on Specification and Design Languages},
year = {2016},
url = {https://ics.jku.at/files/2016FDL_AutomatedRTLtoTLMFaultCorresondence.pdf},
pages = {1--8},
note = {{\bf (Best Paper Candidate)}},
doi = {10.1109/fdl.2016.7880375}
}
@inproceedings{HLGD:2016b,
author = {Vladimir Herdt and Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Compiled Symbolic Simulation for {SystemC}},
booktitle = {International Conference on Computer-Aided Design},
year = {2016},
url = {https://ics.jku.at/files/2016ICCAD_compiled_symbolic_simulation_for_systemc.pdf},
pages = {52:1--52:8},
doi = {10.1145/2966986.2967016}
}
@inproceedings{CSGD:2016b,
author = {Arun Chandrasekharan and Mathias Soeken and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Approximation-aware Rewriting of {AIGs} for Error Tolerant Applications},
booktitle = {International Conference on Computer-Aided Design},
year = {2016},
url = {https://ics.jku.at/files/2016ICCAD_approximation_aware_rewriting.pdf},
pages = {83:1--83:8},
doi = {10.1145/2966986.2967003}
}
@inproceedings{HLGD:2016,
author = {Vladimir Herdt and Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler},
title = {{ParCoSS:} Efficient Parallelized Compiled Symbolic Simulation},
booktitle = {Computer Aided Verification},
pages = {177--183},
year = {2016},
url = {https://ics.jku.at/files/2016CAV_ParCoSS.pdf},
doi = {10.1007/978-3-319-41540-6_10}
}
@inproceedings{SSGD:2016,
author = {Saeideh Shirinzadeh and Mathias Soeken and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Approximate {BDD} Optimization with Prioritized $\epsilon$-Preferred Evolutionary Algorithm},
booktitle = {Genetic and Evolutionary Computation Conference},
pages = {79--80},
year = {2016},
url = {https://ics.jku.at/files/2016gecco_Approx_BDD_Optimization.pdf},
doi = {10.1145/2908961.2908987}
}
@inproceedings{CSGD:2016,
author = {Arun Chandrasekharan and Mathias Soeken and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Precise Error Determination of Approximated Components in Sequential Circuits with Model Checking},
booktitle = {Design Automation Conf.},
pages = {129:1--129:6},
year = {2016},
url = {https://ics.jku.at/files/2016DAC_precise_error_determination_seq_approx.pdf},
doi = {10.1145/2897937.2898069}
}
@inproceedings{SGK+:2016,
author = {Amr Sayed-Ahmed and Daniel Gro{\ss}e and Ulrich K\"uhne and Mathias Soeken and Rolf Drechsler},
title = {Formal Verification of Integer Multipliers by Combining {Gr\"obner} Basis with Logic Reduction},
booktitle = {Design, Automation and Test in Europe},
year = 2016,
url = {https://ics.jku.at/files/2016DATE_Groebner_Basis_w_Logic_Reduction.pdf},
pages = {1048--1053},
note = {{\bf (Best Paper Candidate)}},
doi = {10.3850/9783981537079_0248}
}
@inproceedings{LHGD:2016,
author = {Hoang M. Le and Vladimir Herdt and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Towards Formal Verification of Real-World {SystemC} {TLM} Peripheral Models -- A Case Study},
booktitle = {Design, Automation and Test in Europe},
pages = {1160--1163},
year = 2016,
url = {https://ics.jku.at/files/2016DATE_Towards_FormalVerification_of_RealWorld_SystemC-TLM_PheripheralModels.pdf},
doi = {10.3850/9783981537079_0717}
}
@inproceedings{GZC+:2016,
author = {Fan Gu and Xinqian Zhang and Mingsong Chen and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Quantitative Timing Analysis of {UML} Activity Diagrams Using Statistical Model Checking},
booktitle = {Design, Automation and Test in Europe},
pages = {780--785},
year = 2016,
url = {https://ics.jku.at/files/2016DATE_QuantitativeTimingAnalysis_UML_ActitivtyDiagrams.pdf},
doi = {10.3850/9783981537079_0339}
}
@inproceedings{SGCD:2016,
author = {Mathias Soeken and Daniel Gro{\ss}e and Arun Chandrasekharan and Rolf Drechsler},
title = {{BDD} Minimization for Approximate Computing},
booktitle = {ASP Design Automation Conf.},
pages = {474--479},
year = {2016},
url = {https://ics.jku.at/files/2016ASPDAC_BDDforAC.pdf},
doi = {10.1109/aspdac.2016.7428057}
}
@inproceedings{SKGD:2015,
author = {Amr Sayed-Ahmed and Ulrich K\"uhne and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits},
booktitle = {IEEE Annual Symposium on VLSI},
pages = {1--6},
year = {2015},
url = {https://ics.jku.at/files/2015_isvlsi_multiplier_verification.pdf},
doi = {10.1109/isvlsi.2015.45}
}
@inproceedings{HLGD:2015,
author = {Vladimir Herdt and Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Boosting Sequentialization-based Verification of Multi-Threaded {C} Programs via Symbolic Pruning of Redundant Schedules},
booktitle = {Automated Technology for Verification and Analysis},
pages = {228--233},
year = {2015},
url = {https://ics.jku.at/files/2015_atva_boosting_sequentialization_based_verification.pdf},
doi = {10.1007/978-3-319-24953-7_18}
}
@inproceedings{BVB+:2014,
author = {Andreas Burger and Alexander Viehl and Andreas Braun and Finn Haedicke and Daniel Gro{\ss}e and Oliver Bringmann and Wolfgang Rosenstiel},
title = {Constraint-Based Platform Variants Specification for Early System Verification},
booktitle = {ASP Design Automation Conf.},
pages = {800--805},
year = {2014},
url = {https://ics.jku.at/files/2014_aspdac_cstr-based_platform_variants-specification.pdf},
doi = {10.1109/ASPDAC.2014.6742988}
}
@inproceedings{YWGD:2013,
author = {Shuo Yang and Robert Wille and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Minimal Stimuli Generation in Simulation-Based Verification},
booktitle = {EUROMICRO Symposium on Digital System Design},
pages = {439--444},
year = {2013},
url = {https://ics.jku.at/files/2013_dsd_minimal_stimuli_generation.pdf},
doi = {10.1109/dsd.2013.55}
}
@inproceedings{LGHD:2013,
author = {Hoang M. Le and Daniel Gro{\ss}e and Vladimir Herdt and Rolf Drechsler},
title = {Verifying {SystemC} using an intermediate verification language and symbolic simulation},
booktitle = {Design Automation Conf.},
pages = {116:1--116:6},
year = {2013},
url = {https://ics.jku.at/files/2013DAC_SISSI.pdf},
doi = {10.1145/2463209.2488877}
}
@inproceedings{DGLS:2013,
author = {Rolf Drechsler and Daniel Gro{\ss}e and Hoang M. Le and Andr\'e S\"ulflow},
title = {Synchronized Debugging across Different Abstraction Levels in System Design},
booktitle = {Embedded World Conference},
year = {2013},
url = {https://ics.jku.at/files/2013ewc_synchronized_debugging.pdf}
}
@inproceedings{LGD:2013,
author = {Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Scalable Fault Localization for {SystemC} {TLM} Designs},
booktitle = {Design, Automation and Test in Europe},
pages = {35--38},
year = 2013,
url = {https://ics.jku.at/files/2013date_scalable_faultloc_tlm.pdf},
doi = {10.7873/date.2013.022}
}
@inproceedings{LGD:2012c,
author = {Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler},
title = {From Requirements and Scenarios to {ESL} Design in {SystemC}},
booktitle = {International Symposium on Electronic System Design},
pages = {183--187},
year = 2012,
url = {https://ics.jku.at/files/2012ised_reqascen2sysc_esl.pdf},
doi = {10.1109/ised.2012.36}
}
@inproceedings{OKM+:2012,
author = {Marcio F. S. Oliveira and Christoph Kuznik and Wolfgang M\"uller and Finn Haedicke and Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler and Wolfgang Ecker and Volkan Esen},
title = {The System Verification Methodology for Advanced {TLM} Verification},
booktitle = {IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis},
pages = {313--322},
year = 2012,
url = {https://ics.jku.at/files/2012codesisss_svm_tlm.pdf},
doi = {10.1145/2380445.2380497}
}
@inproceedings{HLGD:2012b,
author = {Finn Haedicke and Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler},
title = {{CRAVE}: An Advanced Constrained RAndom Verification Environment for {SystemC}},
booktitle = {International Symposium on System-on-Chip},
pages = {1--7},
year = 2012,
url = {https://ics.jku.at/files/2012SOC_CRAVE.pdf},
doi = {10.1109/issoc.2012.6376356}
}
@inproceedings{DDG+:2012,
author = {Rolf Drechsler and Melanie Diepenbeck and Daniel Gro{\ss}e and Ulrich K\"uhne and Hoang M. Le and J. Seiter and Mathias Soeken and Robert Wille},
title = {Completeness-Driven Development},
booktitle = {International Conference on Graph Transformation},
pages = {38--50},
year = {2012},
url = {https://ics.jku.at/files/2012icgt_cdd.pdf},
doi = {10.1007/978-3-642-33654-6_3}
}
@inproceedings{MGD:2012b,
author = {Marc Michael and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Localizing Features of {ESL} Models for Design Understanding},
booktitle = {Forum on Specification and Design Languages},
pages = {120--125},
year = 2012,
url = {https://ics.jku.at/files/2012fdl_featurelocalization_esl.pdf}
}
@inproceedings{YWGD:2012,
author = {Shuo Yang and Robert Wille and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Coverage-driven Stimuli Generation},
booktitle = {EUROMICRO Symposium on Digital System Design},
year = 2012,
url = {https://ics.jku.at/files/2012dsd_coverage_driven_stim_gen.pdf},
pages = {525--528},
doi = {10.1109/dsd.2012.37}
}
@inproceedings{HGD:2012,
author = {Finn Haedicke and Daniel Gro{\ss}e and Rolf Drechsler},
title = {A Guiding Coverage Metric for Formal Verification},
booktitle = {Design, Automation and Test in Europe},
pages = {617--622},
year = 2012,
url = {https://ics.jku.at/files/2012date_gcm.pdf},
doi = {10.1109/date.2012.6176546}
}
@inproceedings{MGD:2011,
author = {Marc Michael and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Analyzing Dependability Measures at the {E}lectronic {S}ystem {L}evel},
booktitle = {Forum on Specification and Design Languages},
pages = {1--8},
year = 2011,
url = {https://ics.jku.at/files/2011fdl_dependability_esl.pdf}
}
@inproceedings{BGD:2011b,
author = {Mohamed Bawadekji and Daniel Gro{\ss}e and Rolf Drechsler},
title = {{TLM} Protocol Compliance Checking at the Electronic System Level},
pages = {435--440},
booktitle = {IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems},
year = 2011,
url = {https://ics.jku.at/files/2011ddecs_tlm_protocol_compliance.pdf},
doi = {10.1109/ddecs.2011.5783132}
}
@inproceedings{WSG+:2011b,
author = {Robert Wille and Mathias Soeken and Daniel Gro{\ss}e and E. Sch\"onborn and Rolf Drechsler},
title = {Designing a {RISC} {CPU} in Reversible Logic},
pages = {170--175},
booktitle = {International Symposium on {M}ulti-{V}alued {L}ogic},
year = 2011,
url = {https://ics.jku.at/files/2011_ismvl_reversible_cpu.pdf},
doi = {10.1109/ismvl.2011.39}
}
@inproceedings{GGKD:2011b,
author = {Daniel Gro{\ss}e and M. Gro{\ss} and Ulrich K\"uhne and Rolf Drechsler},
title = {Simulation-based Equivalence Checking between {SystemC} Models at different Levels of Abstraction},
booktitle = {ACM Great Lakes Symposium on VLSI},
pages = {223--228},
year = 2011,
url = {https://ics.jku.at/files/2011glsvlsi-simecTLM.pdf},
doi = {10.1145/1973009.1973054}
}
@inproceedings{GLD:2010b,
author = {Daniel Gro{\ss}e and Hoang M. Le and Rolf Drechsler},
title = {Proving Transaction and System-level Properties of Untimed {SystemC} {TLM} Designs},
booktitle = {ACM \& IEEE International Conference on Formal Methods and Models for Codesign},
pages = {113--122},
year = 2010,
url = {https://ics.jku.at/files/2010MEMOCODE-tlmpc.pdf},
doi = {10.1109/memcod.2010.5558643}
}
@inproceedings{WGHD:2009,
author = {Robert Wille and Daniel Gro{\ss}e and Finn Haedicke and Rolf Drechsler},
title = {{SMT}-based Stimuli Generation in the {SystemC} Verification Library},
booktitle = {Forum on Specification and Design Languages},
pages = {1--6},
year = 2009,
url = {https://ics.jku.at/files/2009fdl_smt-based_stimuli_generation_scv.pdf},
doi = {10.1007/978-90-481-9304-2_14}
}
@inproceedings{SKF+:2009,
author = {Andr\'e S\"ulflow and Ulrich K\"uhne and G\"orschwin Fey and Daniel Gro{\ss}e and Rolf Drechsler},
title = {{WoLFram} - A Word Level Framework for Formal Verification},
booktitle = {IEEE/IFIP International Symposium on Rapid System Prototyping},
pages = {11--17},
year = 2009,
url = {https://ics.jku.at/files/2009-rsp-wolfram.pdf},
doi = {10.1109/rsp.2009.21}
}
@inproceedings{GWKD:2009,
author = {Daniel Gro{\ss}e and Robert Wille and Ulrich K\"uhne and Rolf Drechsler},
title = {Contradictory Antecedent Debugging in Bounded Model Checking},
booktitle = {ACM Great Lakes Symposium on VLSI},
pages = {173--176},
year = 2009,
url = {https://ics.jku.at/files/2009glsvlsi_pc_contradiction.pdf},
doi = {10.1145/1531542.1531586}
}
@inproceedings{WGMD:2009b,
author = {Robert Wille and Daniel Gro{\ss}e and D. Michael Miller and Rolf Drechsler},
title = {Equivalence Checking of Reversible Circuits},
booktitle = {International Symposium on {M}ulti-{V}alued {L}ogic},
pages = {324--330},
year = 2009,
url = {https://ics.jku.at/files/2009_ismvl_rev_ec.pdf},
doi = {10.1109/ismvl.2009.19}
}
@inproceedings{KGD:2009,
author = {Ulrich K\"uhne and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Property Analysis and Design Understanding},
booktitle = {Design, Automation and Test in Europe},
pages = {1246--1249},
year = 2009,
url = {https://ics.jku.at/files/2009DATE_property_analysis.pdf},
doi = {10.1109/date.2009.5090855}
}
@inproceedings{WGF+:2009,
author = {Robert Wille and Daniel Gro{\ss}e and Stefan Frehse and Gerhard W. Dueck and Rolf Drechsler},
title = {Debugging of {T}offoli Networks},
booktitle = {Design, Automation and Test in Europe},
pages = {1284--1289},
year = 2009,
url = {https://ics.jku.at/files/2009_date_tof_dbging.pdf},
doi = {10.1109/date.2009.5090863}
}
@inproceedings{WGDD:2009,
author = {Robert Wille and Daniel Gro{\ss}e and Gerhard W. Dueck and Rolf Drechsler},
title = {Reversible Logic Synthesis with Output Permutation},
booktitle = {{VLSI} Design Conference},
pages = {189--194},
year = 2009,
url = {https://ics.jku.at/files/2009_vlsidesign_swop.pdf},
doi = {10.1109/vlsi.design.2009.40}
}
@inproceedings{GWSD:2008b,
author = {Daniel Gro{\ss}e and Robert Wille and Robert Siegmund and Rolf Drechsler},
title = {Contradiction Analysis for Constraint-based Random Simulation},
booktitle = {Forum on Specification and Design Languages},
pages = {130--135},
year = 2008,
url = {https://ics.jku.at/files/2008_fdl_overconstr_analysis.pdf},
doi = {10.1109/fdl.2008.4641434}
}
@inproceedings{WGSD:2008,
author = {Robert Wille and Daniel Gro{\ss}e and Mathias Soeken and Rolf Drechsler},
title = {Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability},
booktitle = {IEEE Annual Symposium on VLSI},
pages = {411--416},
year = {2008},
url = {https://ics.jku.at/files/2008_isvlsi_optprob.pdf},
doi = {10.1109/isvlsi.2008.82}
}
@inproceedings{WGT+:2008,
author = {Robert Wille and Daniel Gro{\ss}e and L. Teuber and Gerhard W. Dueck and Rolf Drechsler},
title = {{RevLib:} An Online Resource for Reversible Functions and Reversible Circuits},
booktitle = {International Symposium on {M}ulti-{V}alued {L}ogic},
note = {{RevLib} is available at http://www.revlib.org},
pages = {220--225},
year = {2008},
url = {https://ics.jku.at/files/2008_ismvl_revlib.pdf},
doi = {10.1109/ISMVL.2008.43}
}
@inproceedings{GWDD:2008,
author = {Daniel Gro{\ss}e and Robert Wille and Gerhard W. Dueck and Rolf Drechsler},
title = {Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares},
booktitle = {International Symposium on {M}ulti-{V}alued {L}ogic},
pages = {214--219},
year = {2008},
url = {https://ics.jku.at/files/2008_ismvl_sat_syn_elem_rev_gates.pdf},
doi = {10.1109/ISMVL.2008.42}
}
@inproceedings{WLDG:2008,
author = {Robert Wille and Hoang M. Le and Gerhard W. Dueck and Daniel Gro{\ss}e},
title = {Quantified Synthesis of Reversible Logic},
booktitle = {Design, Automation and Test in Europe},
pages = {1015--1020},
year = 2008,
url = {https://ics.jku.at/files/2008_date_qbf_syn_tof.pdf},
doi = {10.1145/1403375.1403620}
}
@inproceedings{WG:2007,
author = {Robert Wille and Daniel Gro{\ss}e},
title = {Fast Exact {Toffoli} Network Synthesis of Reversible Logic},
booktitle = {International Conference on Computer-Aided Design},
pages = {60--64},
year = 2007,
url = {https://ics.jku.at/files/2007_iccad_sword_syn_tof.pdf},
doi = {10.1109/ICCAD.2007.4397244}
}
@inproceedings{WFG+:2007,
author = {Robert Wille and G\"orschwin Fey and Daniel Gro{\ss}e and Stephan Eggersgl\"u{\ss} and Rolf Drechsler},
title = {SWORD: A {SAT} like Prover using Word Level Information},
booktitle = {VLSI of System-on-Chip},
pages = {88--93},
year = 2007,
url = {https://ics.jku.at/files/2007vlsi-soc_sword.pdf},
doi = {10.1109/VLSISOC.2007.4402478}
}
@inproceedings{GPKD:2007,
author = {Daniel Gro{\ss}e and Hernan Peraza and Wolfgang Klingauf and Rolf Drechsler},
title = {Measuring the Quality of a {SystemC} Testbench by using Code Coverage Techniques},
booktitle = {Forum on Specification and Design Languages},
pages = {146--151},
year = 2007,
note = {{\bf (Best Paper Award)}},
url = {https://ics.jku.at/files/2007fdl_tbquality.pdf}
}
@inproceedings{KGD:2007,
author = {Ulrich K\"uhne and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Improving the quality of bounded model checking by means of coverage estimation},
booktitle = {IEEE Annual Symposium on VLSI},
pages = {165--170},
year = {2007},
url = {https://ics.jku.at/files/2007isvlsi-improving_bmc_coverage.pdf},
doi = {10.1109/ISVLSI.2007.57}
}
@inproceedings{AGTD:2007,
author = {Mahsan Amoui and Daniel Gro{\ss}e and Mitchell A. Thornton and Rolf Drechsler},
title = {Evaluation of Toggle Coverage for MVL Circuits Specified in the {SystemVerilog HDL}},
booktitle = {International Symposium on {M}ulti-{V}alued {L}ogic},
pages = {50 (6 pages)},
year = {2007},
url = {https://ics.jku.at/files/2007ismvl_togglecoverage_sv.pdf},
doi = {10.1109/ismvl.2007.19}
}
@inproceedings{GED:2007,
author = {Daniel Gro{\ss}e and R\"udiger Ebendt and Rolf Drechsler},
title = {Improvements for constraint solving in the {SystemC} verification library},
booktitle = {ACM Great Lakes Symposium on VLSI},
year = {2007},
pages = {493--496},
url = {https://ics.jku.at/files/2007glsvlsi_scv_improvements.pdf},
doi = {10.1145/1228784.1228901}
}
@inproceedings{GCDD:2007,
title = {Exact {SAT}-based {Toffoli} Network Synthesis},
author = {Daniel Gro{\ss}e and Xiaobo Chen and Gerhard W. Dueck and Rolf Drechsler},
booktitle = {ACM Great Lakes Symposium on VLSI},
pages = {96--101},
year = 2007,
url = {https://ics.jku.at/files/2007glsvlsi_exact-sat-toffoli.pdf},
doi = {10.1145/1228784.1228812}
}
@inproceedings{GKD:2007,
author = {Daniel Gro{\ss}e and Ulrich K\"uhne and Rolf Drechsler},
title = {Estimating Functional Coverage in Bounded Model Checking},
booktitle = {Design, Automation and Test in Europe},
pages = {1176--1181},
year = {2007},
url = {https://ics.jku.at/files/2007DATE_BMC_coverage.pdf},
doi = {10.1109/date.2007.364454}
}
@inproceedings{GKD:2006,
author = {Daniel Gro{\ss}e and Ulrich K\"uhne and Rolf Drechsler},
title = {HW/SW Co-Verification of Embedded Systems using Bounded Model Checking},
booktitle = {ACM Great Lakes Symposium on VLSI},
pages = {43--48},
year = 2006,
url = {https://ics.jku.at/files/2006glsvlsi_hwsw_coverification.pdf},
doi = {10.1145/1127908.1127920}
}
@inproceedings{FGD:2006,
author = {G\"orschwin Fey and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Avoiding false negatives in formal verification for protocol-driven blocks},
booktitle = {Design, Automation and Test in Europe},
year = {2006},
pages = {1225--1226},
url = {https://ics.jku.at/files/2006date_ip_environment.pdf},
doi = {10.1109/date.2006.244074}
}
@inproceedings{GD:2005c,
author = {Daniel Gro{\ss}e and Rolf Drechsler},
title = {Acceleration of {SAT}-based Iterative Property Checking},
booktitle = {Correct Hardware Design and Verification Methods},
year = 2005,
pages = {349--353},
url = {https://ics.jku.at/files/2005charme_acc_sat_pc.pdf},
doi = {10.1007/11560548_29}
}
@inproceedings{GD:2005b,
author = {Daniel Gro{\ss}e and Rolf Drechsler},
title = {{\em CheckSyC}: An Efficient Property Checker for {RTL} {SystemC} Designs},
booktitle = {IEEE International Symposium on Circuits and Systems},
year = 2005,
pages = {4167--4170},
url = {https://ics.jku.at/files/2005iscas_checksyc.pdf},
doi = {10.1109/iscas.2005.1465549}
}
@inproceedings{PGHD:2004,
author = {Jan Peleska and Daniel Gro{\ss}e and Anne E. Haxthausen and Rolf Drechsler},
title = {Automated Verification For Train Control Systems},
booktitle = {Formal Methods for Automation and Safety in Railway and Automotive Systems},
pages = {252--265},
year = 2004,
url = {https://ics.jku.at/files/2004formsformat_train_verification.pdf}
}
@inproceedings{GD:2004,
author = {Daniel Gro{\ss}e and Rolf Drechsler},
title = {Checkers for {SystemC} Designs},
booktitle = {ACM \& IEEE International Conference on Formal Methods and Models for Codesign},
pages = {171--178},
year = 2004,
url = {https://ics.jku.at/files/2004memocode_checkers_for_systemc_designs.pdf},
doi = {10.1109/memcod.2004.1459851}
}
@inproceedings{GDLA:2003,
author = {Daniel Gro{\ss}e and Rolf Drechsler and Lothar Linhard and Gerhard Angst},
title = {Efficient Automatic Visualization of {SystemC} Designs},
booktitle = {Forum on Specification and Design Languages},
pages = {646--657},
year = 2003,
url = {https://ics.jku.at/files/2003fdl_vis_systemc.pdf},
public = {no}
}
@inproceedings{GD:2003,
author = {Daniel Gro{\ss}e and Rolf Drechsler},
title = {Formal Verification of {LTL} Formulas for {SystemC} Designs},
booktitle = {IEEE International Symposium on Circuits and Systems},
pages = {V:245--V:248},
year = 2003,
url = {https://ics.jku.at/files/2003iscas_ltl_verification_systemc.pdf},
public = {no},
doi = {10.1109/iscas.2003.1206243}
}
@inproceedings{GFD:2003,
author = {Daniel Gro{\ss}e and G\"orschwin Fey and Rolf Drechsler},
title = {Modeling Multi-Valued Circuits in {SystemC}},
booktitle = {International Symposium on {M}ulti-{V}alued {L}ogic},
year = {2003},
url = {https://ics.jku.at/files/2003ismvl_systemc.pdf},
pages = {281--286},
doi = {10.1109/ismvl.2003.1201418}
}
@inproceedings{DG:2002b,
author = {Rolf Drechsler and Daniel Gro{\ss}e},
title = {Reachability Analysis for Formal Verification of {SystemC}},
booktitle = {EUROMICRO Symposium on Digital System Design},
pages = {337--340},
year = 2002,
url = {https://ics.jku.at/files/2002dsd_reach_systemc.pdf},
public = {no},
doi = {10.1109/dsd.2002.1115387}
}
@inproceedings{SDGD:2001,
author = {Frank Schmiedle and Nicole Drechsler and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Priorities in Multi-Objective Optimization for Genetic Programming},
booktitle = {Genetic and Evolutionary Computation Conference},
year = 2001,
pages = {129--136}
}
@inproceedings{SGDB:2001,
author = {Frank Schmiedle and Daniel Gro{\ss}e and Rolf Drechsler and Bernd Becker},
title = {Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics},
booktitle = {International Conference on Computational Intelligence (Fuzzy Days)},
series = {LNCS},
volume = {2206},
year = 2001,
pages = {479--491},
doi = {10.1007/3-540-45493-4_49}
}
@inproceedings{DSGD:2001a,
author = {Nicole Drechsler and Frank Schmiedle and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Heuristic Learning based on Genetic Programming},
booktitle = {European Conference on Genetic Programming},
series = {LNCS},
publisher = {Springer},
volume = 2038,
year = 2001,
pages = {1--10},
doi = {10.1007/3-540-45355-5_1}
}
@inproceedings{SHG:2024,
author = {Manfred Schl{\"{a}}gl and Christoph Hazott and Daniel Gro{\ss}e},
title = {{RISC-V VP++}: Next Generation Open-Source Virtual Prototype},
booktitle = {Workshop on Open-Source Design Automation},
year = 2024,
code = {https://github.com/ics-jku/riscv-vp-plusplus},
url = {https://ics.jku.at/files/2024OSDA_RISCV-VP-plusplus.pdf}
}
@inproceedings{KG:2024b,
author = {Lucas Klemmer and Daniel Gro{\ss}e},
title = {{WSVA:} A {SystemVerilog Assertion} to {WAL} Compiler},
booktitle = {Workshop on Open-Source Design Automation},
year = 2024,
url = {https://ics.jku.at/files/2024OSDA_WSVA.pdf}
}
@inproceedings{HSG:2024b,
author = {Christoph Hazott and Florian St\"ogm\"uller and Daniel Gro{\ss}e},
title = {Leveraging Virtual Prototypes and Metamorphic Testing for Verification of Embedded Graphics Libraries},
booktitle = {ITG/GI/GMM-Workshop ``Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen''},
year = 2024,
url = {https://ics.jku.at/files/2024MBMV_MT-VP-Embedded_Graphics_Libraries.pdf}
}
@inproceedings{RG:2023b,
author = {Katharina Ruep and Daniel Gro{\ss}e},
title = {Fuzz-Testing of {SpinalHDL} Designs},
booktitle = {ITG/GI/GMM-Workshop ``Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen''},
year = 2023,
url = {https://ics.jku.at/files/2023MBMV_Fuzz-testing-of-SpinalHDL-designs.pdf}
}
@inproceedings{KGG:2023,
author = {Lucas Klemmer and Sonja Gurtner and Daniel Gro{\ss}e},
title = {How We Learned to Stop Worrying and Build a {RISC-V VP} with only one Microcode Instruction},
booktitle = {ITG/GI/GMM-Workshop ``Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen''},
year = 2023,
url = {https://ics.jku.at/files/2023MBMV_How-we-learned-to-stop-worrying-and-build-a-RISC-V-VP-with-only-one-microcode-instruction.pdf}
}
@inproceedings{KSM+:2023,
author = {Alexander Konrad and Christoph Scholl and Alireza Mahzoon and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Divider Verification Using Symbolic Computer Algebra and Delayed Don't Care Optimization},
booktitle = {ITG/GI/GMM-Workshop ``Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen''},
year = {2023},
url = {https://ics.jku.at/files/2023MBMV_Divider-verification-using-symbolic-computer-algebra-and-ddco.pdf}
}
@inproceedings{KG:2023,
author = {Lucas Klemmer and Daniel Gro{\ss}e},
title = {Programming Language Assisted Waveform Analysis: A Case Study on the Instruction Performance of {SERV}},
booktitle = {Workshop on Open-Source Design Automation},
year = 2023,
url = {https://ics.jku.at/files/2023OSDA_WAL-instruction-performance-SERV.pdf}
}
@inproceedings{HVE+:2022,
author = {Muhammad Hassan and Thilo V\"ortler and Karsten Einwich and Rolf Drechsler and Daniel Gro{\ss}e},
title = {Towards System-level Assertions for Heterogeneous Systems},
booktitle = {Int'l Workshop on Boolean Problems},
year = 2022,
url = {https://ics.jku.at/files/2022IWSBP_Towards_System-level_Assertions_HeterogenousSystems.pdf}
}
@inproceedings{KG:2022b,
author = {Lucas Klemmer and Daniel Gro{\ss}e},
title = {Programmable Waveform Analysis using the Domain Specific Language {WAL}},
booktitle = {ITG/GI/GMM-Workshop ``Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen''},
year = 2022
}
@inproceedings{PHGD:2021,
title = {{VP}-based {DIFT} for Embedded Binaries: A {RISC-V} Case Study},
author = {Pascal Pieper and Vladimir Herdt and Daniel Gro{\ss}e and Rolf Drechsler},
booktitle = {ITG/GI/GMM-Workshop ``Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen''},
year = {2021}
}
@inproceedings{MGD:2021,
author = {Alireza Mahzoon and Daniel Gro{\ss}e and Rolf Drechsler},
title = {{GenMul}: Generating Architecturally Complex Multipliers to Challenge Formal Verification Tools},
booktitle = {ITG/GI/GMM-Workshop ``Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen''},
year = {2021}
}
@inproceedings{HGD:2020f,
author = {Vladimir Herdt and Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Fuzz-Testing {RISC-V} Simulators},
booktitle = {ITG/GI/GMM-Workshop ``Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen''},
year = {2020}
}
@inproceedings{HGAD:2020,
author = {Muhammad Hassan and Daniel Gro{\ss}e and Ahmad Asghar and Rolf Drechsler},
title = {Coverage-Directed Stimuli Generation for Characterization of {RF} Amplifiers},
booktitle = {GI/ITG Workshop ``Testmethoden und Zuverl\"assigkeit von Schaltungen und Systemen''},
year = {2020}
}
@inproceedings{MGD:2019b,
author = {Alireza Mahzoon and Daniel Gro{\ss}e and Rolf Drechsler},
title = {{GenMul}: Generating Architecturally Complex Multipliers to Challenge Formal Verification Tools},
booktitle = {Int'l Workshop on Logic Synth.},
year = {2019}
}
@inproceedings{WWT+:2019c,
author = {Marcel Walter and Robert Wille and Frank Sill Torres and Daniel Gro{\ss}e and Rolf Drechsler},
title = {fiction: An Open Source Framework for the Design of Field-coupled Nanocomputing Circuits},
booktitle = {Int'l Workshop on Logic Synth.},
year = {2019}
}
@inproceedings{HLGD:2018d,
author = {Vladimir Herdt and Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Evaluation of Power State Cross Coverage in Firmware-Based Power Management},
booktitle = {Embedded Software for Industrial IoTs},
year = {2018}
}
@inproceedings{HLGD:2018c,
author = {Vladimir Herdt and Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Towards Automated Refinement of {TLM} Properties to {RTL}},
booktitle = {ITG/GI/GMM-Workshop ``Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen''},
year = {2018}
}
@inproceedings{LHGD:2017,
author = {Hoang M. Le and Vladimir Herdt and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Revisiting Symbolic Software-implemented Fault Injection},
booktitle = {International ESWEEK Workshop on Resiliency in Embedded Electronic Systems},
year = {2017}
}
@inproceedings{FGD:2017,
author = {Saman Froehlich and Daniel Gro{\ss}e and Rolf Drechsler},
title = {{Exakte BDD Minimierung mit Fehlerschranke f\"ur den Einsatz im Approximate Computing}},
booktitle = {ITG/GI/GMM-Workshop ``Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen''},
year = {2017}
}
@inproceedings{GSD:2016,
author = {Daniel Gro{\ss}e and Kenneth Schmitz and Rolf Drechsler},
title = {Using Lightweight Containers in Hardware/Software Co-Design for Security},
booktitle = {Workshop on Computer-Aided Design and Implementation for Cryptography and Security},
year = {2016}
}
@inproceedings{CGSD:2016,
author = {Arun Chandrasekharan and Daniel Gro{\ss}e and Mathias Soeken and Rolf Drechsler},
title = {Symbolic Error Metric Determination for Approximate Computing},
booktitle = {ITG/GI/GMM-Workshop ``Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen''},
pages = {75--76},
year = {2016}
}
@inproceedings{WLGD:2015,
author = {Aljoscha Windhorst and Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Towards Generating Test Suites with High Functional Coverage for Error Effect Simulation},
booktitle = {International ESWEEK Workshop on Resiliency in Embedded Electronic Systems},
year = {2015}
}
@inproceedings{SGCD:2015,
author = {Mathias Soeken and Daniel Gro{\ss}e and Arun Chandrasekharan and Rolf Drechsler},
title = {Using Binary Decision Diagrams in the Design Flow of Approximate Computing},
booktitle = {Workshop on Approximate Computing},
year = {2015}
}
@inproceedings{WLGD:2014,
author = {Aljoscha Windhorst and Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Funktionale {A}bdeckungsanalyse von {C-Programmen}},
booktitle = {ITG/GI/GMM-Workshop ``Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen''},
pages = {201--204},
year = {2014}
}
@inproceedings{LGHD:2013b,
title = {{SystemC} {V}erifikation mittels symbolischer {S}imulation einer {Z}wischensprache},
author = {Hoang M. Le and Daniel Gro{\ss}e and Vladimir Herdt and Rolf Drechsler},
booktitle = {Electronic Design Automation Workshop},
year = {2013}
}
@inproceedings{DSGD:2013,
author = {Melanie Diepenbeck and Mathias Soeken and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Towards automatic scenario generation from coverage information},
booktitle = {International Workshop on Automation of Software Test},
year = {2013},
pages = {82--88}
}
@inproceedings{RRO+:2012,
title = {Compilation of Methodologies to Speed up the Verification Process at System Level},
author = {Stephan Radke and Steffen R\"ulke and Marcio F. S. Oliveira and Christoph Kuznik and Wolfgang M\"uller and Wolfgang Ecker and Volkan Esen and Simon Hufnagel and Nico Bannow and Helmut Brazdrum and Peter Janssen and Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler and Erhard Fehlauer and Gernot Koch and Andreas Burger and Oliver Bringmann and Wolfgang Rosenstiel and Finn Haedicke and Ralph G\"orgen and Jan-Hendrik Oetjens},
booktitle = {Electronic Design Automation Workshop},
year = {2012},
pages = {57--62}
}
@inproceedings{DSGD:2012,
author = {Melanie Diepenbeck and Mathias Soeken and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Behavior Driven Development for Circuit Design and Verification},
booktitle = {IEEE International High Level Design Validation and Test Workshop},
pages = {9--16},
year = 2012
}
@inproceedings{MGD:2012,
author = {Marc Michael and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Design Understanding by Feature Localization on {ESL}},
booktitle = {9. GMM/ITG/GI-Workshop Cyber-Physical Systems - Enabling Multi-Nature Systems},
pages = {19--24},
year = 2012
}
@inproceedings{LGD:2012,
author = {Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler},
title = {{SystemC-based} {ESL} Verification Flow Integrating Property Checking and Automatic Debugging},
booktitle = {DATE Friday Workshop: OSCI and Accellera Core Technologies for the Next Generation of System-Level Design},
year = 2012
}
@inproceedings{HLGD:2012,
author = {Finn Haedicke and Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler},
title = {{CRAVE}: An Advanced Constrained Random Verification Environment for {SystemC}},
booktitle = {ITG/GI/GMM-Workshop ``Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen''},
pages = {37--48},
year = 2012
}
@inproceedings{LGD:2011,
author = {Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Towards Proving {TLM} Properties with Local Variables},
booktitle = {7th International Workshop on Constraints in Formal Verification (CFV)},
year = 2011
}
@inproceedings{HFF+:2011,
author = {Finn Haedicke and Stefan Frehse and G\"orschwin Fey and Daniel Gro{\ss}e and Rolf Drechsler},
title = {{metaSMT}: Focus on Your Application not on Solver Integration},
booktitle = {DIFTS'11: 1st International workshop on design and implementation of formal tools and systems},
pages = {22--29},
year = 2011
}
@inproceedings{GHK+:2011,
author = {Kim Gr\"uttner and Andreas Herrholz and Ulrich K\"uhne and Daniel Gro{\ss}e and Achim Rettberg and Wolfgang Nebel and Rolf Drechsler},
title = {Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines},
booktitle = {2nd IEEE Workshop on Self-Organizing Real-Time Systems},
pages = {181--188},
year = 2011,
doi = {10.1109/isorcw.2011.27}
}
@inproceedings{BGD:2011,
author = {Mohamed Bawadekji and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Protocol Compliance Checking of {SystemC} {TLM} Models},
booktitle = {8. GMM/ITG/GI-Workshop Cyber-Physical Systems - Enabling Multi-Nature Systems},
pages = {27--32},
year = 2011
}
@inproceedings{GGKD:2011,
author = {Daniel Gro{\ss}e and M. Gro{\ss} and Ulrich K\"uhne and Rolf Drechsler},
title = {Simulation-based Equivalence Checking between {SystemC} Models at different Levels of Abstraction},
booktitle = {ITG/GI/GMM-Workshop ``Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen''},
pages = {269--278},
year = 2011
}
@inproceedings{WSG+:2011,
author = {Robert Wille and Mathias Soeken and Daniel Gro{\ss}e and E. Sch\"onborn and Rolf Drechsler},
title = {Designing a {RISC} {CPU} in Reversible Logic},
booktitle = {ITG/GI/GMM-Workshop ``Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen''},
pages = {249--258},
year = 2011
}
@inproceedings{LGD:2010b,
author = {Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Automatic Fault Localization for {SystemC} {TLM} Designs},
booktitle = {IEEE International Workshop on Microprocessor Test and Verification},
pages = {35--40},
year = 2010,
doi = {10.1109/mtv.2010.15}
}
@inproceedings{LGD:2010,
author = {Hoang M. Le and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Towards Analyzing Functional Coverage in {SystemC} {TLM} Property Checking},
booktitle = {IEEE International High Level Design Validation and Test Workshop},
pages = {67--74},
year = 2010
}
@inproceedings{GLD:2009,
author = {Daniel Gro{\ss}e and Hoang M. Le and Rolf Drechsler},
title = {Induction-based Formal Verification of {SystemC} {TLM} Designs},
booktitle = {IEEE International Workshop on Microprocessor Test and Verification},
pages = {101--106},
year = 2009,
doi = {10.1109/mtv.2009.16}
}
@inproceedings{WGMD:2009,
author = {Robert Wille and Daniel Gro{\ss}e and D. Michael Miller and Rolf Drechsler},
title = {Equivalence Checking of Reversible Circuits},
pages = {67--76},
booktitle = {ITG/GI/GMM-Workshop ``Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen''},
year = 2009
}
@inproceedings{KGD:2008,
author = {Ulrich K\"uhne and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow},
booktitle = {IEEE International Workshop on Microprocessor Test and Verification},
pages = {88--93},
year = 2008,
doi = {10.1109/mtv.2008.17}
}
@inproceedings{WGDD:2008,
author = {Robert Wille and Daniel Gro{\ss}e and Gerhard W. Dueck and Rolf Drechsler},
title = {Reversible Logic Synthesis with Output Permutation},
booktitle = {Int'l Workshop on Boolean Problems},
year = 2008
}
@inproceedings{GWSD:2008,
author = {Daniel Gro{\ss}e and Robert Wille and Robert Siegmund and Rolf Drechsler},
title = {Contradiction Analysis for Constraint-based Random Simulation},
booktitle = {Dresdner Arbeitstagung Schaltungs- und Systementwurf},
pages = {25--30},
year = 2008
}
@inproceedings{GWKD:2008,
author = {Daniel Gro{\ss}e and Robert Wille and Ulrich K\"uhne and Rolf Drechsler},
title = {Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking},
booktitle = {ITG/GI/GMM-Workshop ``Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen''},
year = 2008,
pages = {169--178}
}
@inproceedings{SKW+:2007,
author = {Andr\'e S\"ulflow and Ulrich K\"uhne and Robert Wille and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Evaluation of {SAT} like Proof Techniques for Formal Verification of Word Level Circuits},
booktitle = {IEEE Workshop on RTL and High Level Testing},
year = 2007,
pages = {31--36}
}
@inproceedings{FGE+:2007,
author = {G\"orschwin Fey and Daniel Gro{\ss}e and Stephan Eggersgl\"u{\ss} and Robert Wille and Rolf Drechsler},
title = {Formal Verification on the Word Level using {SAT}-like Proof Techniques},
booktitle = {ITG/GI/GMM-Workshop ``Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen''},
year = 2007,
pages = {165--173}
}
@inproceedings{GCD:2006,
author = {Daniel Gro{\ss}e and Xiaobo Chen and Rolf Drechsler},
title = {Exact {Toffoli} Network Synthesis of Reversible Logic using Boolean Satisfiability},
booktitle = {IEEE Dallas/CAS Workshop},
year = {2006},
pages = {51--54}
}
@inproceedings{KGD:2006,
author = {Ulrich K\"uhne and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Complete Formal Verification of Multi Core Embedded Systems using Bounded Model Checking},
booktitle = {IEEE Dallas/CAS Workshop},
year = {2006},
pages = {147--150}
}
@inproceedings{GKD:2005b,
author = {Daniel Gro{\ss}e and Ulrich K\"uhne and Rolf Drechsler},
title = {HW/SW Co-Verification of Embedded Systems using Bounded Model Checking},
booktitle = {IEEE International Workshop on Microprocessor Test and Verification},
pages = {133--137},
year = 2005,
doi = {10.1109/mtv.2005.12}
}
@inproceedings{KGD:2005,
author = {Sebastian Kinder and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Bounded Model Checking of Tram Control Systems},
booktitle = {TRain Workshop at SEFM2005},
year = 2005
}
@inproceedings{GKD:2005,
title = {{Formale Verifikation des Befehlssatzes eines SystemC Mikroprozessors}},
author = {Daniel Gro{\ss}e and U. K{\"u}hne and Rolf Drechsler},
year = 2005,
booktitle = {GI Jahrestagung (1)},
pages = {308--312},
series = {Lecture Notes in Informatics},
volume = {67}
}
@inproceedings{GD:2005,
author = {Daniel Gro{\ss}e and Rolf Drechsler},
title = {Acceleration of {SAT}-based Iterative Property Checking},
booktitle = {ITG/GI/GMM-Workshop ``Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen''},
year = 2005,
doi = {10.1007/11560548_29}
}
@inproceedings{GKG+:2005,
author = {Daniel Gro{\ss}e and Ulrich K\"uhne and Christian Genz and Frank Schmiedle and Bernd Becker and Rolf Drechsler and Paul Molitor},
title = {{Modellierung eines Mikroprozessors in SystemC}},
booktitle = {ITG/GI/GMM-Workshop ``Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen''},
year = {2005}
}
@inproceedings{DFGG:2005,
author = {Rolf Drechsler and G\"orschwin Fey and Christian Genz and Daniel Gro{\ss}e},
title = {{SyCE}: An Integrated Environment for System Design in {SystemC}},
booktitle = {IEEE International Workshop on Rapid System Prototyping},
year = {2005},
pages = {258--260},
doi = {10.1109/rsp.2005.46}
}
@inproceedings{FGC+:2004,
author = {G\"orschwin Fey and Daniel Gro{\ss}e and Tim Cassens and Christian Genz and Tim Warode and Rolf Drechsler},
title = {{ParSyC: An Efficient {SystemC} Parser}},
booktitle = {Workshop on Synthesis And System Integration of Mixed Information technologies},
year = {2004},
pages = {148--154},
public = {no}
}
@inproceedings{GD:2003c,
author = {Daniel Gro{\ss}e and Rolf Drechsler},
title = {{BDD}-Based Verification of Scalable Designs},
booktitle = {IEEE International High Level Design Validation and Test Workshop},
year = 2003,
pages = {123--128},
public = {yes},
doi = {10.2298/fuee0703367g}
}
@inproceedings{GD:2003d,
author = {Daniel Gro{\ss}e and Rolf Drechsler},
title = {{Formale Verifikation von LTL-Formeln f\"ur SystemC-Beschreibungen}},
booktitle = {ITG/GI/GMM-Workshop ``Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen''},
pages = {229--238},
year = 2003,
public = {yes}
}
@inproceedings{GK:2024,
author = {Daniel Gro{\ss}e and Lucas Klemmer},
booktitle = {Tutorial at DVCon Europe},
title = {Unleash the Full Potential of Your Waveforms: From Extra-functional Analysis to Functional Debug via Programs on Waveforms},
year = {2024}
}
@inproceedings{Gro:2023,
author = {Daniel Gro{\ss}e},
title = {{RISC-V VP++}: Unlocking the vast Linux ecosystem for Open Source {RISC-V} Virtual Prototypes: From Fast Bootup, {VNC}, Vector Extension to {3D}-Games},
booktitle = {SystemC Evolution Day},
year = {2023}
}
@inproceedings{GK:2023,
author = {Daniel Gro{\ss}e and Lucas Klemmer},
title = {Get the Most out of Your Waveforms -- From Non-functional Analysis to Functional Debug via Programs on Waveforms},
booktitle = {Tutorial at Forum on specification \& Design Languages},
year = {2023}
}
@inproceedings{SHG:2023,
author = {Manfred Schl{\"{a}}gl and Christoph Hazott and Daniel Gro{\ss}e},
title = {Recent Developments in Open-source {RISC-V} Virtual Prototypes: From Vector Extensions, Tracing to {3D}-Games},
booktitle = {Special Session at Forum on specification \& Design Languages},
year = {2023},
code = {https://github.com/ics-jku/riscv-vp-plusplus}
}
@inproceedings{GKFG:2023,
author = {Sonja Gurtner and Lucas Klemmer and Mathias Fleury and Daniel Gro{\ss}e},
title = {Replacing {RISC-V} Instructions by Others},
booktitle = {Proc.~of {SAT Competition} 2023 -- Solver and Benchmark Descriptions},
year = 2023
}
@inproceedings{KG:2021c,
author = {Lucas Klemmer and Daniel Gro{\ss}e},
title = {Applying the Four-Eyes Principle to {RISC-V} Processor Verification by Equivalent Program Execution},
booktitle = {4th Workshop on {RISC-V} Activities},
year = {2021}
}
@inproceedings{KG:2021b,
author = {Lucas Klemmer and Daniel Gro{\ss}e},
title = {Programmable Waveform Analysis using {WAL}},
booktitle = {OpenTapeOut Conference},
year = {2021}
}
@inproceedings{HGJ:2020,
author = {Vladimir Herdt and Daniel Gro{\ss}e and Eyck Jentzsch (organizer)},
title = {Cross-Level Compliance Testing and Verification for {RISC-V}, {Speakers: Daniel Gro{\ss}e, Vladimir Herdt}},
booktitle = {Tutorial at DVCon Europe},
year = {2020}
}
@inproceedings{HJGD:2020,
author = {Vladimir Herdt and Eyck Jentzsch and Daniel Gro{\ss}e and Rolf Drechsler},
title = {Efficient {RISC-V} Processor Verification via Cross-Level Testing},
booktitle = {3rd Workshop on {RISC-V} Activities},
year = {2020}
}
@inproceedings{Gro:2019,
author = {Daniel Gro{\ss}e (organizer)},
title = {{RISC-V} based Firmware Design, {Speakers: Christoph Gerum, Vladimir Herdt, Michael Schwarz}},
booktitle = {Special Session at Forum on specification \& Design Languages},
year = {2019}
}
@inproceedings{Gro:2018,
author = {Daniel Gro{\ss}e (organizer)},
title = {Firmware Firmly under Control: New Optimization and Verification Techniques for Application Specific Electronic Systems, {Speakers: Daniel Gro{\ss}e, Manuel Strobel, Daniel M\"uller-Gritschneder, Vladimir Herdt, Tobias Ludwig}},
booktitle = {Tutorial at DVCon Europe},
year = {2018}
}
@inproceedings{Gro:2018b,
author = {Daniel Gro{\ss}e (organizer)},
title = {Embedded Software for the {IoT}: Design, Optimization and Verification, {Speakers: Rafael Stahl, Vladimir Herdt, Michael Schwarz, Aljoscha Kirchner}},
booktitle = {Special Session at Forum on specification \& Design Languages},
year = {2018}
}
@inproceedings{Gro:2017,
author = {Daniel Gro{\ss}e (organizer)},
title = {Automatic Firmware Design for Application-specific Electronic Systems: Opportunities, Challenges and Solutions, {Speakers: Daniel Gro{\ss}e, Joscha Benz, Vladimir Herdt, Martin Dittrich}},
booktitle = {Tutorial at DVCon Europe},
year = {2017}
}
@inproceedings{Gro:2017b,
author = {Daniel Gro{\ss}e (panelist)},
title = {{The WHAT? and WHY? of high-level languages in designing and verifying complex integrated systems - Lets take a formal perspective}},
booktitle = {Panel at Forum on specification \& Design Languages},
year = {2017}
}
@inproceedings{Gro:2016,
author = {Daniel Gro{\ss}e (organizer)},
title = {Reliability and Safety in {VP}-based Embedded System Development, {Speakers: Vladimir Herdt, Bogdan-Andrei Tabacaru}},
booktitle = {Special Session at Forum on specification \& Design Languages},
year = {2016}
}
@inproceedings{GG:2016,
author = {Stephan Gerth and Daniel Gro{\ss}e},
title = {{UVM-SystemC} goes random - Introducing {CRAVE} in {UVM-SystemC}},
booktitle = {Tutorial at DVCon Europe},
year = {2016}
}
@inproceedings{Gro:2014b,
author = {Daniel Gro{\ss}e},
title = {Circuit Design: Slip Schedule or Automate Debug},
booktitle = {DVClub Shanghai: Making Verification Debug More Efficient},
year = {2014}
}
@inproceedings{Gro:2014,
author = {Daniel Gro{\ss}e},
title = {Circuit Design: Slip Schedule or Automate Debug},
booktitle = {International Symposium on {M}ulti-{V}alued {L}ogic},
year = {2014}
}
@inproceedings{GHLD:2011,
author = {Daniel Gro{\ss}e and Finn Haedicke and Hoang M. Le and Rolf Drechsler},
title = {An Advanced Constrained Random Verification Environment for {SystemC}},
booktitle = {24. European SystemC User's Group Meeting (ESCUG)},
year = {2011}
}
@inproceedings{GS:2011,
author = {Daniel Gro{\ss}e and Frank Schirrmeister (organizer)},
title = {{ESL HW/SW} Verification: A Reality Check, {Speakers: Matthias Bauer, Viraphol Chaiyakul, Alan Gatherer, Sandeep Shukla, Daniel Kroening}},
booktitle = {Panel at Design Automation Conference (DAC)},
year = {2011}
}
@inproceedings{GLD:2010,
author = {Daniel Gro{\ss}e and Hoang M. Le and Rolf Drechsler},
title = {Formal Verification of Abstract {SystemC} Models},
booktitle = {Algorithms and Applications for Next Generation SAT Solvers},
year = {2010},
editor = {Bernd Becker and Valeria Bertacco and Rolf Drechsler and Masahiro Fujita},
number = {09461},
series = {Dagstuhl Seminar Proceedings}
}
@inproceedings{BEE+:2010,
author = {Oliver Bringmann and Wolfgang Ecker and Volkan Esen and Erhard Fehlauer and Daniel Gro{\ss}e and Christoph Kuznik and Jan-Hendrik Oetjens and Andreas von Schwerin},
title = {State-of-the-Art and Challenges in {ESL}-Verification},
booktitle = {Full-Day Tutorial at Design, Automation and Test in Europe (DATE)},
year = 2010
}
@inproceedings{GFD:2009,
author = {Daniel Gro{\ss}e and G\"orschwin Fey and Rolf Drechsler},
title = {Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis},
booktitle = {Specification - Transformation - Navigation, Festschrift dedicated to Bernd Krieg-Br\"uckner on Occasion of his 60th Birthday},
year = 2009
}
@phdthesis{Gro:2008,
author = {Daniel Gro{\ss}e},
title = {Quality-Driven Design and Verification Flow for Digital Systems},
school = {Universit\"at Bremen, Bremen, Germany},
year = 2008,
month = oct,
type = {Dissertation}
}
@inproceedings{Gro:2008b,
author = {Daniel Gro{\ss}e},
title = {Using Formal Methods for Verification of Complex Systems},
booktitle = {EDAA/DATE PhD Forum at Design, Automation and Test in Europe},
year = {2008}
}
@inproceedings{GDJ+:2008,
author = {Daniel Gro{\ss}e and Rolf Drechsler and Vasco Jerinic and Jan Langer and Erhard Fehlauer and Frank Roging and Steffen R\"ulke and Frank Dresig and Christian Haufe and Thomas Berndt and Hans-J\"urgen Brand},
title = {{Analysemethoden f\"ur unsichere Anwendungsbedingungen - Beitr\"age von AMD Fraunhofer IIS/EAS, TU Chemnitz und Uni Bremen zu Arbeitspaket 3}},
booktitle = {edaWorkshop (Poster)},
year = 2008
}
@inproceedings{GJL+:2007,
author = {Daniel Gro{\ss}e and Vasco Jerinic and Jan Langer and R. Beckert and Erhard Fehlauer and Frank Roging and Steffen R\"ulke and Hans-J\"urgen Brand and Frank Dresig and Christian Haufe and Thomas Berndt},
title = {{Analysemethoden f\"ur unsichere Anwendungsbedingungen - Beitr\"age von AMD Fraunhofer IIS/EAS, TU Chemnitz und Uni Bremen zu Arbeitspaket 3}},
booktitle = {edaWorkshop (Poster)},
year = 2007
}
@inproceedings{GD:2007b,
author = {Daniel Gro{\ss}e and Rolf Drechsler},
title = {{Debugging in der Constraint-gesteuerten Zufallssimulation}},
booktitle = {URANOS-Workshop Anwendungsrobuster Entwurf nanoelektronischer Systeme},
year = 2007
}
@inproceedings{GLB+:2006,
author = {Daniel Gro{\ss}e and Jan Langer and R. Beckert and H. S\"u{\ss}e and Erhard Fehlauer and Frank Roging and Frank Dresig and Christian Haufe and Thomas Berndt},
title = {{Analysemethoden f\"ur unsichere Anwendungsbedingungen}},
booktitle = {Ekompass-Workshop (Poster)},
year = 2006
}
@inproceedings{GD:2006b,
author = {Daniel Gro{\ss}e and Rolf Drechsler},
title = {{Verifikation mit Constraint-gesteuerter Zufallssimulation}},
booktitle = {URANOS-Workshop Anwendungsrobuster Entwurf nanoelektronischer Systeme},
year = 2006
}
@mastersthesis{Gro:2002,
author = {Daniel Gro{\ss}e},
title = {{Formale Verifikation von SystemC-Beschreibungen}},
year = {2002},
month = aug,
school = {Albert-Ludwigs-Universit\"at, Freiburg, Germany},
type = {Diploma thesis}
}