Publications

Head of institute: Univ.-Prof. Dr. Daniel Große


Books Book Contributions Journals Conferences Workshops Others

Books

[1] Muhammad Hassan, Daniel Große, and Rolf Drechsler. Erweiterte virtuelle Prototypen für heterogene Systeme. Springer, 2024. [ bib | DOI ]
[2] Alireza Mahzoon, Daniel Große, and Rolf Drechsler. Formal Verification of Structurally Complex Multipliers. Springer, 2023. [ bib | DOI ]
[3] Vladimir Herdt, Daniel Große, and Rolf Drechsler. Verbessertes virtuelles Prototyping: Mit RISC-V-Fallstudien. Springer, 2023. [ bib | DOI ]
[4] Muhammad Hassan, Daniel Große, and Rolf Drechsler. Enhanced Virtual Prototyping for Heterogeneous Systems. Springer, 2022. [ bib | DOI ]
[5] Rolf Drechsler and Daniel Große, editors. Recent Findings in Boolean Techniques. Springer, 2021. [ bib | DOI ]
[6] Vladimir Herdt, Daniel Große, and Rolf Drechsler. Enhanced Virtual Prototyping: Featuring RISC-V Case Studies. Springer, 2020. [ bib | DOI ]
[7] Tom J. Kazmierski, Sebastian Steinhorst, and Daniel Große, editors. Languages, Design Methods, and Tools for Electronic System Design – Selected Contributions from FDL 2018. Springer, 2020. [ bib | DOI ]
[8] Daniel Große, Sara Vinco, and Hiren Patel, editors. Languages, Design Methods, and Tools for Electronic System Design – Selected Contributions from FDL 2017. Springer, 2019. [ bib | DOI ]
[9] Arun Chandrasekharan, Daniel Große, and Rolf Drechsler. Design Automation Techniques for Approximation Circuits. Springer, 2018. [ bib | DOI ]
[10] Daniel Große and Rolf Drechsler, editors. Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen. Shaker Verlag, 2017. [ bib ]
[11] Daniel Große and Oliver Bringmann, editors. 8. Workshop Cyber-Physical Systems - Enabling Multi-Nature Systems: domänenübergreifender Entwurf von heterogenen eingebetteten Systemen, 23.-24. Februar 2011. Universität Bremen, 2011. [ bib ]
[12] Daniel Große and Rolf Drechsler. Quality-Driven SystemC Design. Springer, 2010. [ bib | DOI ]
[13] Daniel Große, André Sülflow, and Nicole Drechsler, editors. EXplayN - Strategieoptimierung und Analyse ausgewählter Spielprobleme. Shaker Verlag, 2008. [ bib ]
[14] Daniel Große, Görschwin Fey, and Rolf Drechsler, editors. SATRIX - Algorithmen für Boolesche Erfüllbarkeit. Shaker Verlag, 2007. [ bib ]

Book Contributions

[15] Muhammad Hassan, Thilo Vörtler, Karsten Einwich, Rolf Drechsler, and Daniel Große. Toward system-level assertions for heterogeneous systems. In Rolf Drechsler and Sebastian Huhn, editors, Advanced Boolean Techniques: Selected Papers from the 15th International Workshop on Boolean Problems, pages 67–81. Springer, 2023. [ bib | DOI ]
[16] Alireza Mahzoon, Daniel Große, and Rolf Drechsler. GenMul: Generating architecturally complex multipliers to challenge formal verification tools. In Rolf Drechsler and Daniel Große, editors, Recent Findings in Boolean Techniques, pages 177–191. Springer, 2021. [ bib | DOI ]
[17] Vladimir Herdt, Daniel Große, Hoang M. Le, and Rolf Drechsler. Extensible and configurable RISC-V based virtual prototype. In Tom J. Kazmierski, Sebastian Steinhorst, and Daniel Große, editors, Languages, Design Methods, and Tools for Electronic System Design: Selected Contributions from FDL 2018, pages 115–134. Springer, 2020. [ bib | DOI ]
[18] Saman Froehlich, Daniel Große, and Rolf Drechsler. Approximate memory: Data storage in the context of approximate computing. In Cornelia S. Große and Rolf Drechsler, editors, Information Storage, pages 111–133. Springer, 2019. [ bib | DOI ]
[19] Saman Froehlich, Daniel Große, and Rolf Drechsler. Approximate hardware generation using formal techniques. In Sherief Reda and Muhammad Shafique, editors, Approximate Circuits: Methodologies and CAD, pages 155–174. Springer, 2019. [ bib | DOI ]
[20] Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. Towards early validation of firmware-based power management using virtual prototypes: A constrained random approach. In Daniel Große, Sara Vinco, and Hiren Patel, editors, Languages, Design Methods, and Tools for Electronic System Design: Selected Contributions from FDL 2017, pages 25–44. Springer, 2019. [ bib | DOI ]
[21] Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study. In F. Fummi and R. Wille, editors, Languages, Design Methods, and Tools for Electronic System Design: Selected Contributions from FDL 2016, pages 39–58. Springer, 2018. [ bib | DOI ]
[22] Daniel Große, Hoang M. Le, and Rolf Drechsler. Formal verification of SystemC-based cyber components. In S. Jeschke, C. Brecher, H. Song, and D. B. Rawat, editors, Industrial Internet of Things: Cybermanufacturing Systems, pages 137–167. Springer, 2016. [ bib | DOI ]
[23] Daniel Große, Görschwin Fey, and Rolf Drechsler. Enhanced formal verification flow for circuits integrating debugging and coverage analysis. In R. Ubar, J. Raik, and H. T. Vierhaus, editors, Design and Test Technology for Dependable Systems-on-Chip, pages 119–129. Information Science Reference, 2011. [ bib | DOI ]
[24] Robert Wille, Daniel Große, Finn Haedicke, and Rolf Drechsler. SMT-based stimuli generation in the SystemC verification library. In D. Borrione, editor, Advances in Design Methods from Modeling Languages for Embedded Systems and SoC's: Selected Contributions on Specification, Design, and Verification from FDL 2009, pages 227–244. Springer, 2010. [ bib | DOI ]
[25] Daniel Große. Qualitätsorientierter Entwurfs- und Verifikationsablauf für digitale Systeme. In D. Wagner et al., editor, Ausgezeichnete Informatikdisserationen 2008, volume D-9 of Lecture Notes in Informatics, pages 121–130. Gesellschaft für Informatik, 2009. [ bib ]
[26] Daniel Große, Robert Wille, Robert Siegmund, and Rolf Drechsler. Debugging contradictory constraints in constraint-based random simulation. In M. Radetzki, editor, Languages for Embedded Systems and their Applications: Selected Contributions on Specification, Design, and Verification from FDL'08, pages 273–290. Springer, 2009. [ bib | DOI ]
[27] Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, and Rolf Drechsler. Sword: A SAT like prover using word level information. In R. Reis, V. Mooney, and P. Hasler, editors, VLSI-SoC: Advanced Topics on Systems on a Chip: A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip, pages 175–192. Springer, 2009. [ bib | DOI ]
[28] Daniel Große, Hernan Peraza, Wolfgang Klingauf, and Rolf Drechsler. Measuring the quality of a SystemC testbench by using code coverage techniques. In E. Villar, editor, Embedded Systems Specification and Design Languages: Selected contributions from FDL'07, pages 73–86. Springer, 2008. [ bib | DOI ]
[29] Daniel Große, Robert Siegmund, and Rolf Drechsler. Processor verification. In P. Ienne and R. Leupers, editors, Customizable Embedded Processors, pages 281–302. Elsevier, 2006. [ bib | DOI ]
[30] Rolf Drechsler and Daniel Große. System-level validation using formal techniques. In Bashir M. Al-Hashimi, editor, System-on-Chip: Next Generation Electronics, pages 715–745. The IEE, 2006. [ bib ]

Journals

[31] Christoph Hazott, Florian Stögmüller, and Daniel Große. Using virtual prototypes and metamorphic testing to verify the hardware/software-stack of embedded graphics libraries. Integr., 101, 2025. [ bib | DOI | sourcecode ]
[32] Alexander Konrad, Christoph Scholl, Alireza Mahzoon, Daniel Große, and Rolf Drechsler. Divider verification using symbolic computer algebra and delayed don't care optimization: theory and practical implementation. Formal Methods in System Design: An International Journal, May 2024. [ bib | DOI ]
[33] Lucas Klemmer and Daniel Große. WAVING goodbye to manual waveform analysis in HDL design with WAL. IEEE Transactions on Computer Aided Design of Circuits and Systems, 43(10):3198–3211, 2024. [ bib | DOI | https ]
[34] Alireza Mahzoon, Daniel Große, and Rolf Drechsler. RevSCA-2.0: SCA-based formal verification of non-trivial multipliers using reverse engineering and local vanishing removal. IEEE Transactions on Computer Aided Design of Circuits and Systems, 41(5):1573–1586, 2022. [ bib | DOI | https ]
[35] Niklas Bruns, Vladimir Herdt, Daniel Große, and Rolf Drechsler. Toward RISC-V CSR compliance testing. IEEE Embedded Systems Letters, 13(4):202–205, 2021. [ bib | DOI ]
[36] Vladimir Herdt, Daniel Große, Sören Tempel, and Rolf Drechsler. Adaptive simulation with virtual prototypes in an open-source RISC-V evaluation platform. Journal of Systems Architecture - Embedded Software Design, 116:102135, 2021. [ bib | DOI ]
[37] Buse Ustaoglu, Kenneth Schmitz, Daniel Große, and Rolf Drechsler. ReCoFused partial reconfiguration for secure moving-target countermeasures on FPGAs. SN Applied Sciences, 2(8):1–17, 2020. [ bib | DOI ]
[38] Frank Sill Torres, Pedro Arthur Silva, Geraldo Fontes, Marcel Walter, José Augusto Miranda Nacif, Ricardo Santos Ferreira, Omar Paranaiba Vilela Neto, Jeferson F. Chaves, Robert Wille, Philipp Niemann, Daniel Große, and Rolf Drechsler. On the impact of the synchronization constraint and interconnections in quantum-dot cellular automata. Microprocessors and Microsystems, 76:103109, 2020. [ bib | DOI ]
[39] Vladimir Herdt, Daniel Große, Pascal Pieper, and Rolf Drechsler. RISC-V based virtual prototype: An extensible and configurable platform for the system-level. Journal of Systems Architecture - Embedded Software Design, 109:101756, 2020. [ bib | DOI ]
[40] Marcel Walter, Robert Wille, Daniel Große, Frank Sill Torres, and Rolf Drechsler. Placement and routing for tile-based field-coupled nanocomputing circuits is NP-complete. Journal on Emerging Technologies in Computing Systems, 15(3):29:1–29:10, 2019. [ bib | DOI ]
[41] Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. Combining sequentialization-based verification of multi-threaded C programs with symbolic partial order reduction. Software Tools for Technology Transfer, 21(5):545–565, 2019. [ bib | DOI ]
[42] Mehran Goli, Muhammad Hassan, Daniel Große, and Rolf Drechsler. Security validation of VP-based SoCs using dynamic information flow tracking. it-Information Technology, 61(1):45–58, 2019. [ bib | DOI ]
[43] Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. Verifying SystemC using intermediate verification language and stateful symbolic simulation. IEEE Transactions on Computer Aided Design of Circuits and Systems, 38(7):1359–1372, July 2019. [ bib | DOI ]
[44] Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Daniel Große, and Rolf Drechsler. Behaviour driven development for hardware design. IPSJ Trans. System LSI Design Methodology, 11:29–45, 2018. [ bib | DOI ]
[45] Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, and Görschwin Fey. metaSMT: Focus on your application not on solver integration. Software Tools for Technology Transfer, 19(5):605–621, October 2017. [ bib | DOI ]
[46] Daniel Große, Görschwin Fey, and Rolf Drechsler. Enhanced formal verification flow for circuits integrating debugging and coverage analysis. Electronic Communication of the European Association of Software Science and Technology, 62, 2013. [ bib | DOI ]
[47] Hoang M. Le, Daniel Große, and Rolf Drechsler. Automatic TLM fault localization for SystemC. IEEE Transactions on Computer Aided Design of Circuits and Systems, 31(8):1249–1262, August 2012. [ bib | DOI ]
[48] Robert Wille, Daniel Große, D. Michael Miller, and Rolf Drechsler. Equivalence checking of reversible circuits. Multiple-Valued Logic and Soft Computing, 19(4):361–378, 2012. [ bib | DOI ]
[49] Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, and Rolf Drechsler. Debugging reversible circuits. Integration, the VLSI Journal, 44(1):51–61, January 2011. [ bib | DOI ]
[50] Ulrich Kühne, Daniel Große, and Rolf Drechsler. Towards fully automatic synthesis of embedded software. IEEE Embedded Systems Letters, 2(3):53–57, September 2010. [ bib | DOI ]
[51] Daniel Große, Robert Wille, Gerhard W. Dueck, and Rolf Drechsler. Exact multiple control Toffoli network synthesis with SAT techniques. IEEE Transactions on Computer Aided Design of Circuits and Systems, 28(5):703–715, 2009. [ bib | DOI ]
[52] Daniel Große, Robert Wille, Gerhard W. Dueck, and Rolf Drechsler. Exact synthesis of elementary quantum gate circuits. Multiple-Valued Logic and Soft Computing, 15(4):283–300, 2009. [ bib | DOI ]
[53] Bernd Scholz-Reiter, Michael Lütjen, Carmen Ruthenbeck, Florian Harjes, Rolf Drechsler, and Daniel Große. Formale Verifikation von logistischen Prozessmodellen. ERP Management, 5(4):44–47, 2009. [ bib ]
[54] Daniel Große, Ulrich Kühne, and Rolf Drechsler. Analyzing functional coverage in bounded model checking. IEEE Transactions on Computer Aided Design of Circuits and Systems, 27(7):1305–1314, July 2008. [ bib | DOI ]
[55] Daniel Große and Rolf Drechsler. BDD-based verification of scalable designs. Facta Universitatis. Series: Electronics and Energetics, 20(3):367–379, 2007. [ bib | DOI ]
[56] Rolf Drechsler and Daniel Große. System level validation using formal techniques. IEE Proceedings Computer & Digital Techniques, Special Issue on Embedded Microelectronic Systems: Status and Trends, 152(3):393–406, May 2005. [ bib ]
[57] Daniel Große and Rolf Drechsler. Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC. it+ti, 4:219–226, 2003. [ bib | DOI ]
[58] Frank Schmiedle, Nicole Drechsler, Daniel Große, and Rolf Drechsler. Heuristic learning based on genetic programming. Genetic Programming and Evolvable Machines, 3:363–388, 2002. [ bib | DOI ]

Conferences

[59] Manfred Schlägl and Daniel Große. Fast interpreter-based instruction set simulation for virtual prototypes. In Design, Automation and Test in Europe, 2025. [ bib | sourcecode | .pdf ]
[60] Manfred Schlägl and Daniel Große. Single instruction isolation for RISC-V vector test failures. In International Conference on Computer-Aided Design, 2024. [ bib | sourcecode | .pdf ]
[61] Lucas Klemmer and Daniel Große. An extensible and flexible methodology for analyzing the cache performance of hardware designs. In Forum on Specification and Design Languages, pages 1–8, 2024. [ bib | DOI | .pdf ]
[62] Lucas Klemmer, Frans Skarman, Oscar Gustafsson, and Daniel Große. Surfer: a waveform viewer as dynamic as RISC-V. In RISC-V Summit Europe, 2024. [ bib | website | sourcecode | .pdf ]
[63] Manfred Schlägl and Daniel Große. Bounded load/stores in grammar-based code generation for testing the RISC-V vector extension. In RISC-V Summit Europe, 2024. [ bib | sourcecode | .pdf ]
[64] Christoph Hazott and Daniel Große. Relation coverage: A new paradigm for hardware/software testing. In European Test Symposium, pages 1–4, 2024. [ bib | DOI | sourcecode | .pdf ]
[65] Manfred Schlägl, Moritz Stockinger, and Daniel Große. A RISC-V “V” VP: Unlocking vector processing for evaluation at the system level. In Design, Automation and Test in Europe, pages 1–6, 2024. [ bib | DOI | sourcecode | .pdf ]
[66] Daniel Große, Lucas Klemmer, and Dominik Bonora. Using formal verification methods for optimization of circuits under external constraints. In Design, Automation and Test in Europe, pages 1–6, 2024. [ bib | DOI | .pdf ]
[67] Christoph Hazott, Florian Stögmüller, and Daniel Große. Verifying embedded graphics libraries leveraging virtual prototypes and metamorphic testing. In ASP Design Automation Conf., pages 275–281, 2024. [ bib | DOI | sourcecode | .pdf ]
[68] Lucas Klemmer and Daniel Große. Towards a highly interactive design-debug-verification cycle. In ASP Design Automation Conf., pages 692–697, 2024. [ bib | DOI | .pdf ]
[69] Christoph Hazott and Daniel Große. DSA monitoring framework for HW/SW partitioning of application kernels leveraging VPs. In IEEE Design and Verification Conference and Exhibition Europe, pages 34–41, 2023. [ bib | .pdf ]
[70] Lucas Klemmer, Dominik Bonora, and Daniel Große. Large-scale gatelevel optimization leveraging property checking. In IEEE Design and Verification Conference and Exhibition Europe, pages 86–93, 2023. [ bib | .pdf ]
[71] Frans Skarman, Lucas Klemmer, Oscar Gustafsson, and Daniel Große. Enhancing compiler-driven HDL design with automatic waveform analysis. In Forum on Specification and Design Languages, pages 1–8, 2023. [ bib | DOI | .pdf ]
[72] Lucas Klemmer and Daniel Große. A DSL for visualizing pipelines: A RISC-V case study. In RISC-V Summit Europe, 2023. [ bib | .pdf ]
[73] Manfred Schlägl and Daniel Große. GUI-VP Kit: A RISC-V VP meets Linux graphics - enabling interactive graphical application development. In ACM Great Lakes Symposium on VLSI, pages 599–605, 2023. [ bib | DOI | sourcecode | .pdf ]
[74] Katharina Ruep and Daniel Große. Improving design understanding of processors leveraging datapath clustering. In Design, Automation and Test in Europe, pages 1–2, 2023. [ bib | DOI | .pdf ]
[75] Lucas Klemmer, Eyck Jentzsch, and Daniel Große. Programmable analysis of RISC-V processor simulations using WAL. In Design and Verification Conference and Exhibition Europe, 2022. [ bib | .pdf ]
[76] Muhammad Hassan, Thilo Vörtler, Karsten Einwich, Rolf Drechsler, and Daniel Große. A cross-domain heterogeneous ABV-library for mixed-signal virtual prototypes in SystemC/AMS. In Design and Verification Conference and Exhibition Europe, 2022. [ bib | .pdf ]
[77] Lucas Klemmer, Sonja Gurtner, and Daniel Große. Formal verification of SUBLEQ microcode implementing the RV32I ISA. In Forum on Specification and Design Languages, pages 1–8, 2022. (Best Paper Award). [ bib | DOI | sourcecode | .pdf ]
[78] Alexander Konrad, Christoph Scholl, Alireza Mahzoon, Daniel Große, and Rolf Drechsler. Divider verification using symbolic computer algebra and delayed don't care optimization. In Int'l Conf. on Formal Methods in CAD, pages 108–117, 2022. [ bib | DOI | .pdf ]
[79] Lucas Klemmer and Daniel Große. An exploration platform for microcoded RISC-V cores leveraging the one instruction set computer principle. In IEEE Annual Symposium on VLSI, pages 38–43, 2022. [ bib | DOI | sourcecode | .pdf ]
[80] Lucas Klemmer, Manfred Schlägl, and Daniel Große. RVVRadar: a framework for supporting the programmer in vectorization for RISC-V. In ACM Great Lakes Symposium on VLSI, pages 183–187, 2022. [ bib | DOI | sourcecode | .pdf ]
[81] Niklas Bruns, Vladimir Herdt, Daniel Große, and Rolf Drechsler. Efficient cross-level processor verification using coverage-guided fuzzing. In ACM Great Lakes Symposium on VLSI, pages 97–103, 2022. [ bib | DOI | .pdf ]
[82] Lucas Klemmer and Daniel Große. Waveform-based performance analysis of RISC-V processors: late breaking results. In Design Automation Conf., pages 1404–1405, 2022. [ bib | DOI | .pdf ]
[83] Alireza Mahzoon, Daniel Große, Christoph Scholl, Alexander Konrad, and Rolf Drechsler. Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability. In Design Automation Conf., pages 1183–1188, 2022. [ bib | DOI | .pdf ]
[84] Pascal Pieper, Vladimir Herdt, Daniel Große, and Rolf Drechsler. Verifying SystemC TLM peripherals using modern C++ symbolic execution tools. In Design Automation Conf., pages 1177–1182, 2022. [ bib | DOI | .pdf ]
[85] Katharina Ruep and Daniel Große. SpinalFuzz: Coverage-guided fuzzing for SpinalHDL designs. In European Test Symposium, pages 1–4, 2022. [ bib | DOI | sourcecode | .pdf ]
[86] Lucas Klemmer and Daniel Große. WAL: a novel waveform analysis language for advanced design understanding and debugging. In ASP Design Automation Conf., pages 358–364, 2022. [ bib | DOI | website | sourcecode | .pdf ]
[87] Frank Riese, Vladimir Herdt, Daniel Große, and Rolf Drechsler. Metamorphic testing for processor verification: A RISC-V case study at the instruction level. In VLSI of System-on-Chip, pages 1–6, 2021. [ bib | DOI | .pdf ]
[88] Lucas Klemmer and Daniel Große. EPEX: processor verification by equivalent program execution. In ACM Great Lakes Symposium on VLSI, pages 33–38, 2021. [ bib | DOI | .pdf ]
[89] Lucas Klemmer, Saman Froehlich, Rolf Drechsler, and Daniel Große. XbNN: Enabling CNNs on edge devices by approximate on-chip dot product encoding. In IEEE International Symposium on Circuits and Systems, pages 1–5, 2021. [ bib | DOI | .pdf ]
[90] Christoph Scholl, Alexander Konrad, Alireza Mahzoon, Daniel Große, and Rolf Drechsler. Verifying dividers using symbolic computer algebra and don't care optimization. In Design, Automation and Test in Europe, pages 1110–1115, 2021. [ bib | DOI | .pdf ]
[91] Muhammad Hassan, Daniel Große, and Rolf Drechsler. System level verification of phase-locked loop using metamorphic relations. In Design, Automation and Test in Europe, pages 1378–1381, 2021. (Best Paper Candidate). [ bib | DOI | .pdf ]
[92] Muhammad Hassan, Daniel Große, and Rolf Drechsler. System-level verification of linear and non-linear behaviors of RF amplifiers using metamorphic relations. In ASP Design Automation Conf., pages 761–766, 2021. [ bib | DOI | .pdf ]
[93] Vladimir Herdt, Sören Tempel, Daniel Große, and Rolf Drechsler. Mutation-based compliance testing for RISC-V. In ASP Design Automation Conf., pages 55–60, 2021. [ bib | DOI | .pdf ]
[94] Vladimir Herdt, Daniel Große, Sören Tempel, and Rolf Drechsler. Adaptive simulation with virtual prototypes for RISC-V: Switching between fast and accurate at runtime. In Int'l Conf. on Comp. Design, pages 312–315, 2020. [ bib | DOI | .pdf ]
[95] Tim Meywerk, Marcel Walter, Daniel Große, and Rolf Drechsler. Clustering-guided SMT(LRA) learning. In International Conference on integrated Formal Methods, pages 41–59, 2020. [ bib | DOI | .pdf ]
[96] Tim Meywerk, Marcel Walter, Vladimir Herdt, Jan Kleinekathöfer, Daniel Große, and Rolf Drechsler. Verifying safety properties of robotic plans operating in real-world environments via logic-based environment modeling. In International Symposium On Leveraging Applications of Formal Methods, Verification and Validation, pages 326–347, 2020. [ bib | DOI | .pdf ]
[97] Vladimir Herdt, Daniel Große, Eyck Jentzsch, and Rolf Drechsler. Efficient cross-level testing for processor verification: A RISC-V case-study. In Forum on Specification and Design Languages, pages 1–7, 2020. (Best Paper Award). [ bib | DOI | .pdf ]
[98] Vladimir Herdt, Daniel Große, and Rolf Drechsler. RVX - a tool for concolic testing of embedded binaries targeting RISC-V platforms. In Automated Technology for Verification and Analysis, pages 543–549, 2020. [ bib | DOI | .pdf ]
[99] David Lemma, Mehran Goli, Daniel Große, and Rolf Drechsler. Towards generation of a programmable power management unit at the electronic system level. In IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, pages 1–6, 2020. [ bib | DOI ]
[100] Niklas Bruns, Daniel Große, and Rolf Drechsler. Early verification of ISA extension specifications using deep reinforcement learning. In ACM Great Lakes Symposium on VLSI, pages 297–302, 2020. [ bib | DOI | .pdf ]
[101] Vladimir Herdt, Daniel Große, Jonas Wloka, Tim Güneysu, and Rolf Drechsler. Verification of embedded binaries using coverage-guided fuzzing with SystemC-based virtual prototypes. In ACM Great Lakes Symposium on VLSI, pages 101–106, 2020. [ bib | DOI | .pdf ]
[102] Vladimir Herdt, Daniel Große, and Rolf Drechsler. Closing the RISC-V compliance gap: Looking from the negative testing side. In Design Automation Conf., pages 1–6, 2020. [ bib | DOI | .pdf ]
[103] Pascal Pieper, Vladimir Herdt, Daniel Große, and Rolf Drechsler. Dynamic information flow tracking for embedded binaries using SystemC-based virtual prototypes. In Design Automation Conf., pages 1–6, 2020. [ bib | DOI | .pdf ]
[104] Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, and Rolf Drechsler. Verification for field-coupled nanocomputing circuits. In Design Automation Conf., pages 1–6, 2020. [ bib | DOI | .pdf ]
[105] Saman Froehlich, Lucas Klemmer, Daniel Große, and Rolf Drechsler. ASNet: Introducing approximate hardware to high-level synthesis of neural networks. In International Symposium on Multi-Valued Logic, pages 64–69, 2020. [ bib | DOI | .pdf ]
[106] Alireza Mahzoon, Daniel Große, Christoph Scholl, and Rolf Drechsler. Towards formal verification of optimized and industrial multipliers. In Design, Automation and Test in Europe, pages 544–549, 2020. [ bib | DOI | .pdf ]
[107] Vladimir Herdt, Daniel Große, and Rolf Drechsler. Fast and accurate performance evaluation for RISC-V using virtual prototypes. In Design, Automation and Test in Europe, pages 618–621, 2020. [ bib | DOI | .pdf ]
[108] Vladimir Herdt, Daniel Große, and Rolf Drechsler. Towards specification and testing of RISC-V ISA compliance. In Design, Automation and Test in Europe, pages 995–998, 2020. [ bib | DOI | .pdf ]
[109] Rolf Drechsler and Daniel Große. Ensuring correctness of next generation devices: From reconfigurable to self-learning systems. In Asian Test Symp., pages 159–164, 2019. [ bib | DOI | .pdf ]
[110] Muhammad Hassan, Daniel Große, Thilo Vörtler, Karsten Einwich, and Rolf Drechsler. Functional coverage-driven characterization of RF amplifiers. In Forum on Specification and Design Languages, pages 1–8, 2019. (Best Paper Candidate). [ bib | DOI | .pdf ]
[111] Vladimir Herdt, Daniel Große, Rolf Drechsler, Christoph Gerum, Alexander Jung, Joscha-Joel Benz, Oliver Bringmann, Michael Schwarz, Dominik Stoffel, and Wolfgang Kunz. Systematic RISC-V based firmware design. In Forum on Specification and Design Languages, pages 1–8, 2019. [ bib | DOI | .pdf ]
[112] Tim Meywerk, Marcel Walter, Vladimir Herdt, Daniel Große, and Rolf Drechsler. Towards formal verification of plans for cognition-enabled autonomous robotic agents. In EUROMICRO Symposium on Digital System Design, pages 129–136, 2019. [ bib | DOI | .pdf ]
[113] Buse Ustaoglu, Sebastian Huhn, Frank Sill Torres, Daniel Große, and Rolf Drechsler. SAT-Hard: A learning-based hardware SAT-solver. In EUROMICRO Symposium on Digital System Design, pages 74–81, 2019. [ bib | DOI | .pdf ]
[114] Robert Wille, Marcel Walter, Frank Sill Torres, Daniel Große, and Rolf Drechsler. Ignore clocking constraints: An alternative physical design methodology for field-coupled nanotechnologies. In IEEE Annual Symposium on VLSI, pages 651–656, 2019. [ bib | DOI | .pdf ]
[115] Mehran Goli, Muhammad Hassan, Daniel Große, and Rolf Drechsler. Automated analysis of virtual prototypes at electronic system level. In ACM Great Lakes Symposium on VLSI, pages 307–310, 2019. [ bib | DOI | .pdf ]
[116] Vladimir Herdt, Daniel Große, Hoang M. Le, and Rolf Drechsler. Early concolic testing of embedded binaries with virtual prototypes: A RISC-V case study. In Design Automation Conf., pages 188:1–188:6, 2019. [ bib | DOI | .pdf ]
[117] Alireza Mahzoon, Daniel Große, and Rolf Drechsler. RevSCA: Using reverse engineering to bring light into backward rewriting for big and dirty multipliers. In Design Automation Conf., pages 185:1–185:6, 2019. [ bib | DOI | .pdf ]
[118] Kenneth Schmitz, Buse Ustaoglu, Daniel Große, and Rolf Drechsler. (ReCo)Fuse your PRC or lose security: Finally reliable reconfiguration-based countermeasures on FPGAs. In International Symposium on Applied Reconfigurable Computing, pages 112–126, 2019. [ bib | DOI | .pdf ]
[119] Hoang M. Le, Daniel Große, Niklas Bruns, and Rolf Drechsler. Detection of hardware trojans in SystemC HLS designs via coverage-guided fuzzing. In Design, Automation and Test in Europe, pages 602–605, 2019. [ bib | DOI | .pdf ]
[120] Muhammad Hassan, Daniel Große, Hoang M. Le, and Rolf Drechsler. Data flow testing for SystemC-AMS timed data flow models. In Design, Automation and Test in Europe, pages 366–371, 2019. [ bib | DOI | .pdf ]
[121] Vladimir Herdt, Daniel Große, Hoang M. Le, and Rolf Drechsler. Verifying instruction set simulators using coverage-guided fuzzing. In Design, Automation and Test in Europe, pages 360–365, 2019. [ bib | DOI | .pdf ]
[122] Saman Froehlich, Daniel Große, and Rolf Drechsler. One method - all error-metrics: A three-stage approach for error-metric evaluation in approximate computing. In Design, Automation and Test in Europe, pages 284–287, 2019. [ bib | DOI | .pdf ]
[123] Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. Maximizing power state cross coverage in firmware-based power management. In ASP Design Automation Conf., pages 335–340, 2019. [ bib | DOI | .pdf ]
[124] Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, and Rolf Drechsler. Scalable design for field-coupled nanocomputing circuits. In ASP Design Automation Conf., pages 197–202, 2019. [ bib | DOI | .pdf ]
[125] David Lemma, Mehran Goli, Daniel Große, and Rolf Drechsler. Power intent from initial ESL prototypes: Extracting power management parameters. In Nordic Circuits and Systems Conference, pages 1–6, 2018. [ bib | DOI | .pdf ]
[126] Thilo Vörtler, Karsten Einwich, Muhammad Hassan, and Daniel Große. Using constraints for SystemC AMS design and verification. In Design and Verification Conference and Exhibition Europe, 2018. (Best Paper Award). [ bib | .pdf ]
[127] Vladimir Herdt, Daniel Große, Hoang M. Le, and Rolf Drechsler. Extensible and configurable RISC-V based virtual prototype. In Forum on Specification and Design Languages, pages 5–16, 2018. [ bib | DOI | .pdf ]
[128] Alireza Mahzoon, Daniel Große, and Rolf Drechsler. PolyCleaner: clean your polynomials before backward rewriting to verify million-gate multipliers. In International Conference on Computer-Aided Design, pages 129:1–129:8, 2018. (Best Paper Award). [ bib | DOI | .pdf ]
[129] Saman Froehlich, Daniel Große, and Rolf Drechsler. Towards reversed approximate hardware design. In EUROMICRO Symposium on Digital System Design, pages 665–671, 2018. [ bib | DOI | .pdf ]
[130] Frank Sill Torres, Robert Wille, Marcel Walter, Philipp Niemann, Daniel Große, and Rolf Drechsler. Evaluating the impact of interconnections in quantum-dot cellular automata. In EUROMICRO Symposium on Digital System Design, pages 649–656, 2018. [ bib | DOI | .pdf ]
[131] Frank Sill Torres, Marcel Walter, Robert Wille, Daniel Große, and Rolf Drechsler. Synchronization of clocked field-coupled circuits. In International Conference on Nanotechnology, 2018. [ bib | DOI | .pdf ]
[132] Alireza Mahzoon, Daniel Große, and Rolf Drechsler. Combining symbolic computer algebra and boolean satisfiability for automatic debugging and fixing of complex multipliers. In IEEE Annual Symposium on VLSI, pages 351–356, 2018. [ bib | DOI | .pdf ]
[133] Kenneth Schmitz, Oliver Keszöcze, Jurij Schmidt, Daniel Große, and Rolf Drechsler. Towards dynamic execution environment for system security protection against hardware flaws. In IEEE Annual Symposium on VLSI, pages 557–562, 2018. [ bib | DOI | .pdf ]
[134] David Lemma, Daniel Große, and Rolf Drechsler. Natural language based power domain partitioning. In IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, pages 101–106, 2018. [ bib | DOI | .pdf ]
[135] Buse Ustaoglu, Sebastian Huhn, Daniel Große, and Rolf Drechsler. SAT-Lancer: a hardware SAT-solver for self-verification. In ACM Great Lakes Symposium on VLSI, pages 479–482, 2018. [ bib | DOI | .pdf ]
[136] Muhammad Hassan, Daniel Große, Hoang M. Le, Thilo Vörtler, Karsten Einwich, and Rolf Drechsler. Testbench qualification for SystemC-AMS timed data flow models. In Design, Automation and Test in Europe, pages 857–860, 2018. [ bib | DOI | .pdf ]
[137] Saman Froehlich, Daniel Große, and Rolf Drechsler. Approximate hardware generation using symbolic computer algebra employing Gröbner basis. In Design, Automation and Test in Europe, pages 889–892, 2018. [ bib | DOI | .pdf ]
[138] Marcel Walter, Robert Wille, Daniel Große, Frank Sill Torres, and Rolf Drechsler. An exact method for design exploration of Quantum-dot Cellular Automata. In Design, Automation and Test in Europe, pages 503–508, 2018. [ bib | DOI | .pdf ]
[139] Hoang M. Le, Vladimir Herdt, Daniel Große, and Rolf Drechsler. Resiliency evaluation via symbolic fault injection on intermediate code. In Design, Automation and Test in Europe, pages 845–850, 2018. [ bib | DOI | .pdf ]
[140] Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. Towards fully automated TLM-to-RTL property refinement. In Design, Automation and Test in Europe, pages 1508–1511, 2018. [ bib | DOI | .pdf ]
[141] Arun Chandrasekharan, Stephan Eggersglüß, Daniel Große, and Rolf Drechsler. Approximation-aware testing for approximate circuits. In ASP Design Automation Conf., pages 239–244, 2018. [ bib | DOI | .pdf ]
[142] Rolf Drechsler and Daniel Große. Verifying next generation electronic systems. In International Conference on Infocom Technologies and Unmanned Systems, pages 6–10, 2017. [ bib | DOI | .pdf ]
[143] Arun Chandrasekharan, Daniel Große, and Rolf Drechsler. Yise - a novel framework for boolean networks using Y-inverter graphs. In ACM & IEEE International Conference on Formal Methods and Models for Codesign, pages 114–117, 2017. [ bib | DOI | .pdf ]
[144] Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. Towards early validation of firmware-based power management using virtual prototypes: A constrained random approach. In Forum on Specification and Design Languages, pages 1–8, 2017. [ bib | DOI | .pdf ]
[145] Rehab Massoud, Jannis Stoppe, Daniel Große, and Rolf Drechsler. Semi-formal cycle-accurate temporal execution traces reconstruction. In International Conference on Formal Modelling and Analysis of Timed Systems, pages 335–351, 2017. [ bib | DOI | .pdf ]
[146] Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. Early SoC security validation by VP-based static information flow analysis. In International Conference on Computer-Aided Design, pages 400–407, 2017. [ bib | DOI | .pdf ]
[147] Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, and Rolf Drechsler. An adaptive prioritized ε-preferred evolutionary algorithm for approximate BDD optimization. In Genetic and Evolutionary Computation Conference, pages 1232–1239, 2017. [ bib | DOI | .pdf ]
[148] Arun Chandrasekharan, Daniel Große, and Rolf Drechsler. ProACt: a processor for high performance on-demand approximate computing. In ACM Great Lakes Symposium on VLSI, pages 463–466, 2017. [ bib | DOI | .pdf ]
[149] Saman Froehlich, Daniel Große, and Rolf Drechsler. Error bounded exact BDD minimization in approximate computing. In International Symposium on Multi-Valued Logic, pages 254–259, 2017. [ bib | DOI | .pdf ]
[150] Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Mingsong Chen, Daniel Große, and Rolf Drechsler. Data flow testing for virtual prototypes. In Design, Automation and Test in Europe, pages 380–385, 2017. [ bib | DOI | .pdf ]
[151] Kenneth Schmitz, Arun Chandrasekharan, Jonas Gomes Filho, Daniel Große, and Rolf Drechsler. Trust is good, control is better: Hardware-based instruction-replacement for reliable processor-IPs. In ASP Design Automation Conf., pages 57–62, 2017. [ bib | DOI | .pdf ]
[152] Daniel Große, Hoang M. Le, Muhammad Hassan, and Rolf Drechsler. Guided lightweight software test qualification for IP integration using virtual prototypes. In Int'l Conf. on Comp. Design, pages 606–613, 2016. [ bib | DOI | .pdf ]
[153] Amr Sayed-Ahmed, Daniel Große, Mathias Soeken, and Rolf Drechsler. Equivalence checking using Gröbner bases. In Int'l Conf. on Formal Methods in CAD, pages 169–176, 2016. [ bib | DOI | .pdf ]
[154] Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study. In Forum on Specification and Design Languages, pages 1–8, 2016. (Best Paper Candidate). [ bib | DOI | .pdf ]
[155] Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. Compiled symbolic simulation for SystemC. In International Conference on Computer-Aided Design, pages 52:1–52:8, 2016. [ bib | DOI | .pdf ]
[156] Arun Chandrasekharan, Mathias Soeken, Daniel Große, and Rolf Drechsler. Approximation-aware rewriting of AIGs for error tolerant applications. In International Conference on Computer-Aided Design, pages 83:1–83:8, 2016. [ bib | DOI | .pdf ]
[157] Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. ParCoSS: efficient parallelized compiled symbolic simulation. In Computer Aided Verification, pages 177–183, 2016. [ bib | DOI | .pdf ]
[158] Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, and Rolf Drechsler. Approximate BDD optimization with prioritized ε-preferred evolutionary algorithm. In Genetic and Evolutionary Computation Conference, pages 79–80, 2016. [ bib | DOI | .pdf ]
[159] Arun Chandrasekharan, Mathias Soeken, Daniel Große, and Rolf Drechsler. Precise error determination of approximated components in sequential circuits with model checking. In Design Automation Conf., pages 129:1–129:6, 2016. [ bib | DOI | .pdf ]
[160] Amr Sayed-Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, and Rolf Drechsler. Formal verification of integer multipliers by combining Gröbner basis with logic reduction. In Design, Automation and Test in Europe, pages 1048–1053, 2016. (Best Paper Candidate). [ bib | DOI | .pdf ]
[161] Hoang M. Le, Vladimir Herdt, Daniel Große, and Rolf Drechsler. Towards formal verification of real-world SystemC TLM peripheral models – a case study. In Design, Automation and Test in Europe, pages 1160–1163, 2016. [ bib | DOI | .pdf ]
[162] Fan Gu, Xinqian Zhang, Mingsong Chen, Daniel Große, and Rolf Drechsler. Quantitative timing analysis of UML activity diagrams using statistical model checking. In Design, Automation and Test in Europe, pages 780–785, 2016. [ bib | DOI | .pdf ]
[163] Mathias Soeken, Daniel Große, Arun Chandrasekharan, and Rolf Drechsler. BDD minimization for approximate computing. In ASP Design Automation Conf., pages 474–479, 2016. [ bib | DOI | .pdf ]
[164] Amr Sayed-Ahmed, Ulrich Kühne, Daniel Große, and Rolf Drechsler. Recurrence relations revisited: Scalable verification of bit level multiplier circuits. In IEEE Annual Symposium on VLSI, pages 1–6, 2015. [ bib | DOI | .pdf ]
[165] Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. Boosting sequentialization-based verification of multi-threaded C programs via symbolic pruning of redundant schedules. In Automated Technology for Verification and Analysis, pages 228–233, 2015. [ bib | DOI | .pdf ]
[166] Andreas Burger, Alexander Viehl, Andreas Braun, Finn Haedicke, Daniel Große, Oliver Bringmann, and Wolfgang Rosenstiel. Constraint-based platform variants specification for early system verification. In ASP Design Automation Conf., pages 800–805, 2014. [ bib | DOI | .pdf ]
[167] Shuo Yang, Robert Wille, Daniel Große, and Rolf Drechsler. Minimal stimuli generation in simulation-based verification. In EUROMICRO Symposium on Digital System Design, pages 439–444, 2013. [ bib | DOI | .pdf ]
[168] Hoang M. Le, Daniel Große, Vladimir Herdt, and Rolf Drechsler. Verifying SystemC using an intermediate verification language and symbolic simulation. In Design Automation Conf., pages 116:1–116:6, 2013. [ bib | DOI | .pdf ]
[169] Rolf Drechsler, Daniel Große, Hoang M. Le, and André Sülflow. Synchronized debugging across different abstraction levels in system design. In Embedded World Conference, 2013. [ bib | .pdf ]
[170] Hoang M. Le, Daniel Große, and Rolf Drechsler. Scalable fault localization for SystemC TLM designs. In Design, Automation and Test in Europe, pages 35–38, 2013. [ bib | DOI | .pdf ]
[171] Hoang M. Le, Daniel Große, and Rolf Drechsler. From requirements and scenarios to ESL design in SystemC. In International Symposium on Electronic System Design, pages 183–187, 2012. [ bib | DOI | .pdf ]
[172] Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Müller, Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler, Wolfgang Ecker, and Volkan Esen. The system verification methodology for advanced TLM verification. In IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pages 313–322, 2012. [ bib | DOI | .pdf ]
[173] Finn Haedicke, Hoang M. Le, Daniel Große, and Rolf Drechsler. CRAVE: An advanced constrained random verification environment for SystemC. In International Symposium on System-on-Chip, pages 1–7, 2012. [ bib | DOI | .pdf ]
[174] Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang M. Le, J. Seiter, Mathias Soeken, and Robert Wille. Completeness-driven development. In International Conference on Graph Transformation, pages 38–50, 2012. [ bib | DOI | .pdf ]
[175] Marc Michael, Daniel Große, and Rolf Drechsler. Localizing features of ESL models for design understanding. In Forum on Specification and Design Languages, pages 120–125, 2012. [ bib | .pdf ]
[176] Shuo Yang, Robert Wille, Daniel Große, and Rolf Drechsler. Coverage-driven stimuli generation. In EUROMICRO Symposium on Digital System Design, pages 525–528, 2012. [ bib | DOI | .pdf ]
[177] Finn Haedicke, Daniel Große, and Rolf Drechsler. A guiding coverage metric for formal verification. In Design, Automation and Test in Europe, pages 617–622, 2012. [ bib | DOI | .pdf ]
[178] Marc Michael, Daniel Große, and Rolf Drechsler. Analyzing dependability measures at the Electronic System Level. In Forum on Specification and Design Languages, pages 1–8, 2011. [ bib | .pdf ]
[179] Mohamed Bawadekji, Daniel Große, and Rolf Drechsler. TLM protocol compliance checking at the electronic system level. In IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, pages 435–440, 2011. [ bib | DOI | .pdf ]
[180] Robert Wille, Mathias Soeken, Daniel Große, E. Schönborn, and Rolf Drechsler. Designing a RISC CPU in reversible logic. In International Symposium on Multi-Valued Logic, pages 170–175, 2011. [ bib | DOI | .pdf ]
[181] Daniel Große, M. Groß, Ulrich Kühne, and Rolf Drechsler. Simulation-based equivalence checking between SystemC models at different levels of abstraction. In ACM Great Lakes Symposium on VLSI, pages 223–228, 2011. [ bib | DOI | .pdf ]
[182] Daniel Große, Hoang M. Le, and Rolf Drechsler. Proving transaction and system-level properties of untimed SystemC TLM designs. In ACM & IEEE International Conference on Formal Methods and Models for Codesign, pages 113–122, 2010. [ bib | DOI | .pdf ]
[183] Robert Wille, Daniel Große, Finn Haedicke, and Rolf Drechsler. SMT-based stimuli generation in the SystemC verification library. In Forum on Specification and Design Languages, pages 1–6, 2009. [ bib | DOI | .pdf ]
[184] André Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, and Rolf Drechsler. WoLFram - a word level framework for formal verification. In IEEE/IFIP International Symposium on Rapid System Prototyping, pages 11–17, 2009. [ bib | DOI | .pdf ]
[185] Daniel Große, Robert Wille, Ulrich Kühne, and Rolf Drechsler. Contradictory antecedent debugging in bounded model checking. In ACM Great Lakes Symposium on VLSI, pages 173–176, 2009. [ bib | DOI | .pdf ]
[186] Robert Wille, Daniel Große, D. Michael Miller, and Rolf Drechsler. Equivalence checking of reversible circuits. In International Symposium on Multi-Valued Logic, pages 324–330, 2009. [ bib | DOI | .pdf ]
[187] Ulrich Kühne, Daniel Große, and Rolf Drechsler. Property analysis and design understanding. In Design, Automation and Test in Europe, pages 1246–1249, 2009. [ bib | DOI | .pdf ]
[188] Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, and Rolf Drechsler. Debugging of Toffoli networks. In Design, Automation and Test in Europe, pages 1284–1289, 2009. [ bib | DOI | .pdf ]
[189] Robert Wille, Daniel Große, Gerhard W. Dueck, and Rolf Drechsler. Reversible logic synthesis with output permutation. In VLSI Design Conference, pages 189–194, 2009. [ bib | DOI | .pdf ]
[190] Daniel Große, Robert Wille, Robert Siegmund, and Rolf Drechsler. Contradiction analysis for constraint-based random simulation. In Forum on Specification and Design Languages, pages 130–135, 2008. [ bib | DOI | .pdf ]
[191] Robert Wille, Daniel Große, Mathias Soeken, and Rolf Drechsler. Using higher levels of abstraction for solving optimization problems by boolean satisfiability. In IEEE Annual Symposium on VLSI, pages 411–416, 2008. [ bib | DOI | .pdf ]
[192] Robert Wille, Daniel Große, L. Teuber, Gerhard W. Dueck, and Rolf Drechsler. RevLib: an online resource for reversible functions and reversible circuits. In International Symposium on Multi-Valued Logic, pages 220–225, 2008. RevLib is available at http://www.revlib.org. [ bib | DOI | .pdf ]
[193] Daniel Große, Robert Wille, Gerhard W. Dueck, and Rolf Drechsler. Exact synthesis of elementary quantum gate circuits for reversible functions with don't cares. In International Symposium on Multi-Valued Logic, pages 214–219, 2008. [ bib | DOI | .pdf ]
[194] Robert Wille, Hoang M. Le, Gerhard W. Dueck, and Daniel Große. Quantified synthesis of reversible logic. In Design, Automation and Test in Europe, pages 1015–1020, 2008. [ bib | DOI | .pdf ]
[195] Robert Wille and Daniel Große. Fast exact Toffoli network synthesis of reversible logic. In International Conference on Computer-Aided Design, pages 60–64, 2007. [ bib | DOI | .pdf ]
[196] Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, and Rolf Drechsler. Sword: A SAT like prover using word level information. In VLSI of System-on-Chip, pages 88–93, 2007. [ bib | DOI | .pdf ]
[197] Daniel Große, Hernan Peraza, Wolfgang Klingauf, and Rolf Drechsler. Measuring the quality of a SystemC testbench by using code coverage techniques. In Forum on Specification and Design Languages, pages 146–151, 2007. (Best Paper Award). [ bib | .pdf ]
[198] Ulrich Kühne, Daniel Große, and Rolf Drechsler. Improving the quality of bounded model checking by means of coverage estimation. In IEEE Annual Symposium on VLSI, pages 165–170, 2007. [ bib | DOI | .pdf ]
[199] Mahsan Amoui, Daniel Große, Mitchell A. Thornton, and Rolf Drechsler. Evaluation of toggle coverage for mvl circuits specified in the SystemVerilog HDL. In International Symposium on Multi-Valued Logic, page 50 (6 pages), 2007. [ bib | DOI | .pdf ]
[200] Daniel Große, Rüdiger Ebendt, and Rolf Drechsler. Improvements for constraint solving in the SystemC verification library. In ACM Great Lakes Symposium on VLSI, pages 493–496, 2007. [ bib | DOI | .pdf ]
[201] Daniel Große, Xiaobo Chen, Gerhard W. Dueck, and Rolf Drechsler. Exact SAT-based Toffoli network synthesis. In ACM Great Lakes Symposium on VLSI, pages 96–101, 2007. [ bib | DOI | .pdf ]
[202] Daniel Große, Ulrich Kühne, and Rolf Drechsler. Estimating functional coverage in bounded model checking. In Design, Automation and Test in Europe, pages 1176–1181, 2007. [ bib | DOI | .pdf ]
[203] Daniel Große, Ulrich Kühne, and Rolf Drechsler. Hw/sw co-verification of embedded systems using bounded model checking. In ACM Great Lakes Symposium on VLSI, pages 43–48, 2006. [ bib | DOI | .pdf ]
[204] Görschwin Fey, Daniel Große, and Rolf Drechsler. Avoiding false negatives in formal verification for protocol-driven blocks. In Design, Automation and Test in Europe, pages 1225–1226, 2006. [ bib | DOI | .pdf ]
[205] Daniel Große and Rolf Drechsler. Acceleration of SAT-based iterative property checking. In Correct Hardware Design and Verification Methods, pages 349–353, 2005. [ bib | DOI | .pdf ]
[206] Daniel Große and Rolf Drechsler. CheckSyC: An efficient property checker for RTL SystemC designs. In IEEE International Symposium on Circuits and Systems, pages 4167–4170, 2005. [ bib | DOI | .pdf ]
[207] Jan Peleska, Daniel Große, Anne E. Haxthausen, and Rolf Drechsler. Automated verification for train control systems. In Formal Methods for Automation and Safety in Railway and Automotive Systems, pages 252–265, 2004. [ bib | .pdf ]
[208] Daniel Große and Rolf Drechsler. Checkers for SystemC designs. In ACM & IEEE International Conference on Formal Methods and Models for Codesign, pages 171–178, 2004. [ bib | DOI | .pdf ]
[209] Daniel Große, Rolf Drechsler, Lothar Linhard, and Gerhard Angst. Efficient automatic visualization of SystemC designs. In Forum on Specification and Design Languages, pages 646–657, 2003. [ bib | .pdf ]
[210] Daniel Große and Rolf Drechsler. Formal verification of LTL formulas for SystemC designs. In IEEE International Symposium on Circuits and Systems, pages V:245–V:248, 2003. [ bib | DOI | .pdf ]
[211] Daniel Große, Görschwin Fey, and Rolf Drechsler. Modeling multi-valued circuits in SystemC. In International Symposium on Multi-Valued Logic, pages 281–286, 2003. [ bib | DOI | .pdf ]
[212] Rolf Drechsler and Daniel Große. Reachability analysis for formal verification of SystemC. In EUROMICRO Symposium on Digital System Design, pages 337–340, 2002. [ bib | DOI | .pdf ]
[213] Frank Schmiedle, Nicole Drechsler, Daniel Große, and Rolf Drechsler. Priorities in multi-objective optimization for genetic programming. In Genetic and Evolutionary Computation Conference, pages 129–136, 2001. [ bib ]
[214] Frank Schmiedle, Daniel Große, Rolf Drechsler, and Bernd Becker. Too much knowledge hurts: Acceleration of genetic programs for learning heuristics. In International Conference on Computational Intelligence (Fuzzy Days), volume 2206 of LNCS, pages 479–491, 2001. [ bib | DOI ]
[215] Nicole Drechsler, Frank Schmiedle, Daniel Große, and Rolf Drechsler. Heuristic learning based on genetic programming. In European Conference on Genetic Programming, volume 2038 of LNCS, pages 1–10. Springer, 2001. [ bib | DOI ]

Workshops

[216] Manfred Schlägl, Christoph Hazott, and Daniel Große. RISC-V VP++: Next generation open-source virtual prototype. In Workshop on Open-Source Design Automation, 2024. [ bib | sourcecode | .pdf ]
[217] Lucas Klemmer and Daniel Große. WSVA: a SystemVerilog Assertion to WAL compiler. In Workshop on Open-Source Design Automation, 2024. [ bib | .pdf ]
[218] Christoph Hazott, Florian Stögmüller, and Daniel Große. Leveraging virtual prototypes and metamorphic testing for verification of embedded graphics libraries. In ITG/GI/GMM-Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, 2024. [ bib | .pdf ]
[219] Katharina Ruep and Daniel Große. Fuzz-testing of SpinalHDL designs. In ITG/GI/GMM-Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, 2023. [ bib | .pdf ]
[220] Lucas Klemmer, Sonja Gurtner, and Daniel Große. How we learned to stop worrying and build a RISC-V VP with only one microcode instruction. In ITG/GI/GMM-Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, 2023. [ bib | .pdf ]
[221] Alexander Konrad, Christoph Scholl, Alireza Mahzoon, Daniel Große, and Rolf Drechsler. Divider verification using symbolic computer algebra and delayed don't care optimization. In ITG/GI/GMM-Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, 2023. [ bib | .pdf ]
[222] Lucas Klemmer and Daniel Große. Programming language assisted waveform analysis: A case study on the instruction performance of SERV. In Workshop on Open-Source Design Automation, 2023. [ bib | .pdf ]
[223] Muhammad Hassan, Thilo Vörtler, Karsten Einwich, Rolf Drechsler, and Daniel Große. Towards system-level assertions for heterogeneous systems. In Int'l Workshop on Boolean Problems, 2022. [ bib | .pdf ]
[224] Lucas Klemmer and Daniel Große. Programmable waveform analysis using the domain specific language WAL. In ITG/GI/GMM-Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, 2022. [ bib ]
[225] Pascal Pieper, Vladimir Herdt, Daniel Große, and Rolf Drechsler. VP-based DIFT for embedded binaries: A RISC-V case study. In ITG/GI/GMM-Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, 2021. [ bib ]
[226] Alireza Mahzoon, Daniel Große, and Rolf Drechsler. GenMul: Generating architecturally complex multipliers to challenge formal verification tools. In ITG/GI/GMM-Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, 2021. [ bib ]
[227] Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. Fuzz-testing RISC-V simulators. In ITG/GI/GMM-Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, 2020. [ bib ]
[228] Muhammad Hassan, Daniel Große, Ahmad Asghar, and Rolf Drechsler. Coverage-directed stimuli generation for characterization of RF amplifiers. In GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, 2020. [ bib ]
[229] Alireza Mahzoon, Daniel Große, and Rolf Drechsler. GenMul: Generating architecturally complex multipliers to challenge formal verification tools. In Int'l Workshop on Logic Synth., 2019. [ bib ]
[230] Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, and Rolf Drechsler. fiction: An open source framework for the design of field-coupled nanocomputing circuits. In Int'l Workshop on Logic Synth., 2019. [ bib ]
[231] Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. Evaluation of power state cross coverage in firmware-based power management. In Embedded Software for Industrial IoTs, 2018. [ bib ]
[232] Vladimir Herdt, Hoang M. Le, Daniel Große, and Rolf Drechsler. Towards automated refinement of TLM properties to RTL. In ITG/GI/GMM-Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, 2018. [ bib ]
[233] Hoang M. Le, Vladimir Herdt, Daniel Große, and Rolf Drechsler. Revisiting symbolic software-implemented fault injection. In International ESWEEK Workshop on Resiliency in Embedded Electronic Systems, 2017. [ bib ]
[234] Saman Froehlich, Daniel Große, and Rolf Drechsler. Exakte BDD Minimierung mit Fehlerschranke für den Einsatz im Approximate Computing. In ITG/GI/GMM-Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, 2017. [ bib ]
[235] Daniel Große, Kenneth Schmitz, and Rolf Drechsler. Using lightweight containers in hardware/software co-design for security. In Workshop on Computer-Aided Design and Implementation for Cryptography and Security, 2016. [ bib ]
[236] Arun Chandrasekharan, Daniel Große, Mathias Soeken, and Rolf Drechsler. Symbolic error metric determination for approximate computing. In ITG/GI/GMM-Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, pages 75–76, 2016. [ bib ]
[237] Aljoscha Windhorst, Hoang M. Le, Daniel Große, and Rolf Drechsler. Towards generating test suites with high functional coverage for error effect simulation. In International ESWEEK Workshop on Resiliency in Embedded Electronic Systems, 2015. [ bib ]
[238] Mathias Soeken, Daniel Große, Arun Chandrasekharan, and Rolf Drechsler. Using binary decision diagrams in the design flow of approximate computing. In Workshop on Approximate Computing, 2015. [ bib ]
[239] Aljoscha Windhorst, Hoang M. Le, Daniel Große, and Rolf Drechsler. Funktionale Abdeckungsanalyse von C-Programmen. In ITG/GI/GMM-Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, pages 201–204, 2014. [ bib ]
[240] Hoang M. Le, Daniel Große, Vladimir Herdt, and Rolf Drechsler. SystemC Verifikation mittels symbolischer Simulation einer Zwischensprache. In Electronic Design Automation Workshop, 2013. [ bib ]
[241] Melanie Diepenbeck, Mathias Soeken, Daniel Große, and Rolf Drechsler. Towards automatic scenario generation from coverage information. In International Workshop on Automation of Software Test, pages 82–88, 2013. [ bib ]
[242] Stephan Radke, Steffen Rülke, Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Müller, Wolfgang Ecker, Volkan Esen, Simon Hufnagel, Nico Bannow, Helmut Brazdrum, Peter Janssen, Hoang M. Le, Daniel Große, Rolf Drechsler, Erhard Fehlauer, Gernot Koch, Andreas Burger, Oliver Bringmann, Wolfgang Rosenstiel, Finn Haedicke, Ralph Görgen, and Jan-Hendrik Oetjens. Compilation of methodologies to speed up the verification process at system level. In Electronic Design Automation Workshop, pages 57–62, 2012. [ bib ]
[243] Melanie Diepenbeck, Mathias Soeken, Daniel Große, and Rolf Drechsler. Behavior driven development for circuit design and verification. In IEEE International High Level Design Validation and Test Workshop, pages 9–16, 2012. [ bib ]
[244] Marc Michael, Daniel Große, and Rolf Drechsler. Design understanding by feature localization on ESL. In 9. GMM/ITG/GI-Workshop Cyber-Physical Systems - Enabling Multi-Nature Systems, pages 19–24, 2012. [ bib ]
[245] Hoang M. Le, Daniel Große, and Rolf Drechsler. SystemC-based ESL verification flow integrating property checking and automatic debugging. In DATE Friday Workshop: OSCI and Accellera Core Technologies for the Next Generation of System-Level Design, 2012. [ bib ]
[246] Finn Haedicke, Hoang M. Le, Daniel Große, and Rolf Drechsler. CRAVE: An advanced constrained random verification environment for SystemC. In ITG/GI/GMM-Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, pages 37–48, 2012. [ bib ]
[247] Hoang M. Le, Daniel Große, and Rolf Drechsler. Towards proving TLM properties with local variables. In 7th International Workshop on Constraints in Formal Verification (CFV), 2011. [ bib ]
[248] Finn Haedicke, Stefan Frehse, Görschwin Fey, Daniel Große, and Rolf Drechsler. metaSMT: Focus on your application not on solver integration. In DIFTS'11: 1st International workshop on design and implementation of formal tools and systems, pages 22–29, 2011. [ bib ]
[249] Kim Grüttner, Andreas Herrholz, Ulrich Kühne, Daniel Große, Achim Rettberg, Wolfgang Nebel, and Rolf Drechsler. Towards dependability-aware design of hardware systems using extended program state machines. In 2nd IEEE Workshop on Self-Organizing Real-Time Systems, pages 181–188, 2011. [ bib | DOI ]
[250] Mohamed Bawadekji, Daniel Große, and Rolf Drechsler. Protocol compliance checking of SystemC TLM models. In 8. GMM/ITG/GI-Workshop Cyber-Physical Systems - Enabling Multi-Nature Systems, pages 27–32, 2011. [ bib ]
[251] Daniel Große, M. Groß, Ulrich Kühne, and Rolf Drechsler. Simulation-based equivalence checking between SystemC models at different levels of abstraction. In ITG/GI/GMM-Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, pages 269–278, 2011. [ bib ]
[252] Robert Wille, Mathias Soeken, Daniel Große, E. Schönborn, and Rolf Drechsler. Designing a RISC CPU in reversible logic. In ITG/GI/GMM-Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, pages 249–258, 2011. [ bib ]
[253] Hoang M. Le, Daniel Große, and Rolf Drechsler. Automatic fault localization for SystemC TLM designs. In IEEE International Workshop on Microprocessor Test and Verification, pages 35–40, 2010. [ bib | DOI ]
[254] Hoang M. Le, Daniel Große, and Rolf Drechsler. Towards analyzing functional coverage in SystemC TLM property checking. In IEEE International High Level Design Validation and Test Workshop, pages 67–74, 2010. [ bib ]
[255] Daniel Große, Hoang M. Le, and Rolf Drechsler. Induction-based formal verification of SystemC TLM designs. In IEEE International Workshop on Microprocessor Test and Verification, pages 101–106, 2009. [ bib | DOI ]
[256] Robert Wille, Daniel Große, D. Michael Miller, and Rolf Drechsler. Equivalence checking of reversible circuits. In ITG/GI/GMM-Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, pages 67–76, 2009. [ bib ]
[257] Ulrich Kühne, Daniel Große, and Rolf Drechsler. Property analysis and design understanding in a quality-driven bounded model checking flow. In IEEE International Workshop on Microprocessor Test and Verification, pages 88–93, 2008. [ bib | DOI ]
[258] Robert Wille, Daniel Große, Gerhard W. Dueck, and Rolf Drechsler. Reversible logic synthesis with output permutation. In Int'l Workshop on Boolean Problems, 2008. [ bib ]
[259] Daniel Große, Robert Wille, Robert Siegmund, and Rolf Drechsler. Contradiction analysis for constraint-based random simulation. In Dresdner Arbeitstagung Schaltungs- und Systementwurf, pages 25–30, 2008. [ bib ]
[260] Daniel Große, Robert Wille, Ulrich Kühne, and Rolf Drechsler. Using contradiction analysis for antecedent debugging in bounded model checking. In ITG/GI/GMM-Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, pages 169–178, 2008. [ bib ]
[261] André Sülflow, Ulrich Kühne, Robert Wille, Daniel Große, and Rolf Drechsler. Evaluation of SAT like proof techniques for formal verification of word level circuits. In IEEE Workshop on RTL and High Level Testing, pages 31–36, 2007. [ bib ]
[262] Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, and Rolf Drechsler. Formal verification on the word level using SAT-like proof techniques. In ITG/GI/GMM-Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, pages 165–173, 2007. [ bib ]
[263] Daniel Große, Xiaobo Chen, and Rolf Drechsler. Exact Toffoli network synthesis of reversible logic using boolean satisfiability. In IEEE Dallas/CAS Workshop, pages 51–54, 2006. [ bib ]
[264] Ulrich Kühne, Daniel Große, and Rolf Drechsler. Complete formal verification of multi core embedded systems using bounded model checking. In IEEE Dallas/CAS Workshop, pages 147–150, 2006. [ bib ]
[265] Daniel Große, Ulrich Kühne, and Rolf Drechsler. Hw/sw co-verification of embedded systems using bounded model checking. In IEEE International Workshop on Microprocessor Test and Verification, pages 133–137, 2005. [ bib | DOI ]
[266] Sebastian Kinder, Daniel Große, and Rolf Drechsler. Bounded model checking of tram control systems. In TRain Workshop at SEFM2005, 2005. [ bib ]
[267] Daniel Große, U. Kühne, and Rolf Drechsler. Formale Verifikation des Befehlssatzes eines SystemC Mikroprozessors. In GI Jahrestagung (1), volume 67 of Lecture Notes in Informatics, pages 308–312, 2005. [ bib ]
[268] Daniel Große and Rolf Drechsler. Acceleration of SAT-based iterative property checking. In ITG/GI/GMM-Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, 2005. [ bib | DOI ]
[269] Daniel Große, Ulrich Kühne, Christian Genz, Frank Schmiedle, Bernd Becker, Rolf Drechsler, and Paul Molitor. Modellierung eines Mikroprozessors in SystemC. In ITG/GI/GMM-Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, 2005. [ bib ]
[270] Rolf Drechsler, Görschwin Fey, Christian Genz, and Daniel Große. SyCE: An integrated environment for system design in SystemC. In IEEE International Workshop on Rapid System Prototyping, pages 258–260, 2005. [ bib | DOI ]
[271] Görschwin Fey, Daniel Große, Tim Cassens, Christian Genz, Tim Warode, and Rolf Drechsler. ParSyC: An Efficient SystemC Parser. In Workshop on Synthesis And System Integration of Mixed Information technologies, pages 148–154, 2004. [ bib ]
[272] Daniel Große and Rolf Drechsler. BDD-based verification of scalable designs. In IEEE International High Level Design Validation and Test Workshop, pages 123–128, 2003. [ bib | DOI ]
[273] Daniel Große and Rolf Drechsler. Formale Verifikation von LTL-Formeln für SystemC-Beschreibungen. In ITG/GI/GMM-Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, pages 229–238, 2003. [ bib ]

Others

[274] Daniel Große and Lucas Klemmer. Unleash the full potential of your waveforms: From extra-functional analysis to functional debug via programs on waveforms. In Tutorial at DVCon Europe, 2024. [ bib ]
[275] Daniel Große. RISC-V VP++: Unlocking the vast linux ecosystem for open source RISC-V virtual prototypes: From fast bootup, VNC, vector extension to 3D-games. In SystemC Evolution Day, 2023. [ bib ]
[276] Daniel Große and Lucas Klemmer. Get the most out of your waveforms – from non-functional analysis to functional debug via programs on waveforms. In Tutorial at Forum on specification & Design Languages, 2023. [ bib ]
[277] Manfred Schlägl, Christoph Hazott, and Daniel Große. Recent developments in open-source RISC-V virtual prototypes: From vector extensions, tracing to 3D-games. In Special Session at Forum on specification & Design Languages, 2023. [ bib | sourcecode ]
[278] Sonja Gurtner, Lucas Klemmer, Mathias Fleury, and Daniel Große. Replacing RISC-V instructions by others. In Proc. of SAT Competition 2023 – Solver and Benchmark Descriptions, 2023. [ bib ]
[279] Lucas Klemmer and Daniel Große. Applying the four-eyes principle to RISC-V processor verification by equivalent program execution. In 4th Workshop on RISC-V Activities, 2021. [ bib ]
[280] Lucas Klemmer and Daniel Große. Programmable waveform analysis using WAL. In OpenTapeOut Conference, 2021. [ bib ]
[281] Vladimir Herdt, Daniel Große, and Eyck Jentzsch (organizer). Cross-level compliance testing and verification for RISC-V, Speakers: Daniel Große, Vladimir Herdt. In Tutorial at DVCon Europe, 2020. [ bib ]
[282] Vladimir Herdt, Eyck Jentzsch, Daniel Große, and Rolf Drechsler. Efficient RISC-V processor verification via cross-level testing. In 3rd Workshop on RISC-V Activities, 2020. [ bib ]
[283] Daniel Große (organizer). RISC-V based firmware design, Speakers: Christoph Gerum, Vladimir Herdt, Michael Schwarz. In Special Session at Forum on specification & Design Languages, 2019. [ bib ]
[284] Daniel Große (organizer). Firmware firmly under control: New optimization and verification techniques for application specific electronic systems, Speakers: Daniel Große, Manuel Strobel, Daniel Müller-Gritschneder, Vladimir Herdt, Tobias Ludwig. In Tutorial at DVCon Europe, 2018. [ bib ]
[285] Daniel Große (organizer). Embedded software for the IoT: Design, optimization and verification, Speakers: Rafael Stahl, Vladimir Herdt, Michael Schwarz, Aljoscha Kirchner. In Special Session at Forum on specification & Design Languages, 2018. [ bib ]
[286] Daniel Große (organizer). Automatic firmware design for application-specific electronic systems: Opportunities, challenges and solutions, Speakers: Daniel Große, Joscha Benz, Vladimir Herdt, Martin Dittrich. In Tutorial at DVCon Europe, 2017. [ bib ]
[287] Daniel Große (panelist). The WHAT? and WHY? of high-level languages in designing and verifying complex integrated systems - Lets take a formal perspective. In Panel at Forum on specification & Design Languages, 2017. [ bib ]
[288] Daniel Große (organizer). Reliability and safety in VP-based embedded system development, Speakers: Vladimir Herdt, Bogdan-Andrei Tabacaru. In Special Session at Forum on specification & Design Languages, 2016. [ bib ]
[289] Stephan Gerth and Daniel Große. UVM-SystemC goes random - introducing CRAVE in UVM-SystemC. In Tutorial at DVCon Europe, 2016. [ bib ]
[290] Daniel Große. Circuit design: Slip schedule or automate debug. In DVClub Shanghai: Making Verification Debug More Efficient, 2014. [ bib ]
[291] Daniel Große. Circuit design: Slip schedule or automate debug. In International Symposium on Multi-Valued Logic, 2014. [ bib ]
[292] Daniel Große, Finn Haedicke, Hoang M. Le, and Rolf Drechsler. An advanced constrained random verification environment for SystemC. In 24. European SystemC User's Group Meeting (ESCUG), 2011. [ bib ]
[293] Daniel Große and Frank Schirrmeister (organizer). ESL HW/SW verification: A reality check, Speakers: Matthias Bauer, Viraphol Chaiyakul, Alan Gatherer, Sandeep Shukla, Daniel Kroening. In Panel at Design Automation Conference (DAC), 2011. [ bib ]
[294] Daniel Große, Hoang M. Le, and Rolf Drechsler. Formal verification of abstract SystemC models. In Bernd Becker, Valeria Bertacco, Rolf Drechsler, and Masahiro Fujita, editors, Algorithms and Applications for Next Generation SAT Solvers, number 09461 in Dagstuhl Seminar Proceedings, 2010. [ bib ]
[295] Oliver Bringmann, Wolfgang Ecker, Volkan Esen, Erhard Fehlauer, Daniel Große, Christoph Kuznik, Jan-Hendrik Oetjens, and Andreas von Schwerin. State-of-the-art and challenges in ESL-verification. In Full-Day Tutorial at Design, Automation and Test in Europe (DATE), 2010. [ bib ]
[296] Daniel Große, Görschwin Fey, and Rolf Drechsler. Enhanced formal verification flow for circuits integrating debugging and coverage analysis. In Specification - Transformation - Navigation, Festschrift dedicated to Bernd Krieg-Brückner on Occasion of his 60th Birthday, 2009. [ bib ]
[297] Daniel Große. Quality-Driven Design and Verification Flow for Digital Systems. Dissertation, Universität Bremen, Bremen, Germany, October 2008. [ bib ]
[298] Daniel Große. Using formal methods for verification of complex systems. In EDAA/DATE PhD Forum at Design, Automation and Test in Europe, 2008. [ bib ]
[299] Daniel Große, Rolf Drechsler, Vasco Jerinic, Jan Langer, Erhard Fehlauer, Frank Roging, Steffen Rülke, Frank Dresig, Christian Haufe, Thomas Berndt, and Hans-Jürgen Brand. Analysemethoden für unsichere Anwendungsbedingungen - Beiträge von AMD Fraunhofer IIS/EAS, TU Chemnitz und Uni Bremen zu Arbeitspaket 3. In edaWorkshop (Poster), 2008. [ bib ]
[300] Daniel Große, Vasco Jerinic, Jan Langer, R. Beckert, Erhard Fehlauer, Frank Roging, Steffen Rülke, Hans-Jürgen Brand, Frank Dresig, Christian Haufe, and Thomas Berndt. Analysemethoden für unsichere Anwendungsbedingungen - Beiträge von AMD Fraunhofer IIS/EAS, TU Chemnitz und Uni Bremen zu Arbeitspaket 3. In edaWorkshop (Poster), 2007. [ bib ]
[301] Daniel Große and Rolf Drechsler. Debugging in der Constraint-gesteuerten Zufallssimulation. In URANOS-Workshop Anwendungsrobuster Entwurf nanoelektronischer Systeme, 2007. [ bib ]
[302] Daniel Große, Jan Langer, R. Beckert, H. Süße, Erhard Fehlauer, Frank Roging, Frank Dresig, Christian Haufe, and Thomas Berndt. Analysemethoden für unsichere Anwendungsbedingungen. In Ekompass-Workshop (Poster), 2006. [ bib ]
[303] Daniel Große and Rolf Drechsler. Verifikation mit Constraint-gesteuerter Zufallssimulation. In URANOS-Workshop Anwendungsrobuster Entwurf nanoelektronischer Systeme, 2006. [ bib ]
[304] Daniel Große. Formale Verifikation von SystemC-Beschreibungen. Diploma thesis, Albert-Ludwigs-Universität, Freiburg, Germany, August 2002. [ bib ]