Research

RISC-V

RISC-V related approaches spanning from virtual prototypes to gate level

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SystemC

Approaches for IEEE SystemC, the language for system-level design

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Waveform Analysis Language (WAL)

A programming language for complex waveform analysis and EDA tool development

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Symbolic Computer Algebra (SCA)

Formal verification of hard arithmetic circuits using SCA

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Research Interests

• Electronic Design Automation (EDA)
• Open Source EDA Tools
• Instruction Set Architecture RISC-V
• Modeling (SystemC, (System)Verilog, VHDL, Alternative HDLs)
• Virtual Prototpying, Transaction Level Modeling (TLM), Electronic System Level (ESL)
• Analog Mixed Signal (AMS)
• Simulation-based verification (UVM, Constrained Random Verification)
• Formal verification (Model Checking, Equivalence Checking, Symbolic Execution)
• Symbolic Computer Algebra (SCA)
• (Functional) coverage
• Debugging
• Approximate Computing
• Algorithms and data structures (SMT, SAT, BDDs)
• Emerging technologies

Research Websites/GitHub Projects of the Institute

• Waveform Analysis Language (WAL): https://wal-lang.org and https://github.com/ics-jku/wal
• Formal RISC-V ISA model: https://github.com/ics-jku/epex-formal-rv32-model
• Open source RISC-V VP++: https://github.com/ics-jku/riscv-vp-plusplus
• RISC-V approaches: www.systemc-verification.org/risc-v
• Virtual Prototyping/SystemC tools & verification: www.systemc-verification.org
• AMS verification: www.systemc-verification.org/ams
• Symbolic Computer Algebra: www.sca-verification.org
• Multiplier generator GenMul: www.sca-verification.org/genmul