Teaching

KV Hardware Design

Lecturer:Daniel Große, Lucas Klemmer, Lukas Burgholzer, Gerold Fink
Credits:4,5 ECTS, 3 SWSt
Registration:KUSSS

Objectives

Obtaining an overview of the main steps in the design of circuits and systems as well as receiving basic knowledge in digital chip design using the hardware description language VHDL.

Lecture

  • Design of Systems
  • Target Architectures for HW/SW Systems
  • Allocation, Binding, Scheduling
  • Partitioning
  • Hardware Design
  • Abstraction Levels
  • Hardware Description Languages (VHDL, SystemC)
  • Synthesis
  • Verification
  • Debugging
  • Test

Exercise

  • HDLs
  • Design flow for FPGA applications
  • Exercises for practical utilization of the newly learned skills

Place and Time

  • Lecture: Wednesday, 12:00 – 14:30 S5 101
  • Language: English

More Information

In case of any questions, please contact daniel.grosse@jku.at.