SE Seminar in Computational Engineering:
Open-Source Hardware, RISC-V and Design Automation

Lecturer:Daniel Große, Katharina Ruep
Credits:3 ECTS, 2 SWSt


Open-source hardware and the Instruction Set Architecture (ISA) RISC-V are getting more and more traction, both from academia as well as from industry. This allows to design your own system including your own processor. The software side also emerges fast due to the wide and growing RISC-V ecosystem. At the same time open-source Electronic Design Automation (EDA) tools (e.g. for synthesis, verification, etc.) are becoming more and more powerful. In this spectrum we will consider the design, verification and creation of a system based on open-source hardware and open-source EDA tools.


In this seminar, we will consider recent research in the above mentioned fields. Possible topics include (but are not limited to):

  • Design of systems including a RISC-V processor
  • (Formal) verification
  • Synthesis
  • Open-source design flows (e.g. Efabless Open MPW Program using Skywater PDK with support from Google)
  • And much more

The Institute for Complex Systems (ICS) is very active in the field of EDA and RISC-V, see our recent conference publications.


The seminar will be conducted as a block. We will have an initial meeting in October where we will discuss the details (also the seminar schedule). For participation in the seminar please register in KUSSS. We will then contact all interested students with a proposal for the initial meeting. In case of any questions, please contact daniel.grosse@jku.at.