[1]
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Manfred Schlägl and Daniel Große.
Fast interpreter-based instruction set simulation for virtual
prototypes.
In Design, Automation and Test in Europe Conference (DATE),
2025.
[ bib |
sourcecode |
.pdf ]
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[2]
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Manfred Schlägl and Daniel Große.
Single instruction isolation for RISC-V vector test failures.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD), 2024.
[ bib |
sourcecode |
.pdf ]
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[3]
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Manfred Schlägl and Daniel Große.
Bounded load/stores in grammar-based code generation for testing the
RISC-V vector extension.
In RISC-V Summit Europe, 2024.
[ bib |
sourcecode |
.pdf ]
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[4]
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Manfred Schlägl, Moritz Stockinger, and Daniel Große.
A RISC-V “V” VP: Unlocking vector processing for evaluation at
the system level.
In Design, Automation and Test in Europe Conference (DATE),
pages 1–6, 2024.
[ bib |
DOI |
sourcecode |
.pdf ]
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[5]
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Manfred Schlägl and Daniel Große.
GUI-VP Kit: A RISC-V VP meets Linux graphics - enabling
interactive graphical application development.
In ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 599–605,
2023.
[ bib |
DOI |
sourcecode |
.pdf ]
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[6]
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Lucas Klemmer, Manfred Schlägl, and Daniel Große.
RVVRadar: a framework for supporting the programmer in
vectorization for RISC-V.
In ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 183–187,
2022.
[ bib |
DOI |
sourcecode |
.pdf ]
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