SystemC Verification

This page summarizes our activities around SystemC, a C++ class library standardized by IEEE for modeling hardware/software systems. The result are so-called Virtual Prototypes (VPs) which leverage Transaction Level Modeling (TLM) to achieve orders of mangitue faster simulation performance compared to RTL.

Besides our VP-based approaches, please also watch out for our activites around our Constrained RAndom Verification Environment (CRAVE). For the full list on our work around RISC-V, please visit:

Snake demo on HiFive1 RISC-V VP vs real Hardware
GUI-VP Kit and networking: Loading a web page from the Internet with a web-browser running on Linux and X.Org
GUI-VP Kit real-time interaction: Playing a Linux port of a classic first-person 3D-game

New: Our virtual prototype RISCV-VP++ is available now at our ICS GitHub. RISCV VP++ allows very fast Linux bootup, VNC, Vector Extension (RVV), 3D-game demos, and more! Take a look at the GUI-VP Kit to get a quick and easy-to-use starting point for experimenting with RISCV-VP++, Linux and interactive graphical applications.

VP Model

VP Model & Cross-Level Verification

Software/Firmware Verification

Compliance Testing