Dr. Lucas Klemmer

Portrait of Dr. Lucas Klemmer

Dr. Lucas Klemmer

Science Park 4, 3rd floor, room 0321
lucas.klemmer@jku.at
+43 732 2468 4562

Publications

Journals

[1] Lucas Klemmer and Daniel Große. WAVING goodbye to manual waveform analysis in HDL design with WAL. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 43(10):3198–3211, 2024. [ bib | DOI | http ]

Conferences

[2] Lucas Klemmer and Daniel Große. An extensible and flexible methodology for analyzing the cache performance of hardware designs. In Forum on Specification and Design Languages (FDL), pages 1–8, 2024. [ bib | DOI | .pdf ]
[3] Lucas Klemmer, Frans Skarman, Oscar Gustafsson, and Daniel Große. Surfer: a waveform viewer as dynamic as RISC-V. In RISC-V Summit Europe, 2024. [ bib | website | sourcecode | .pdf ]
[4] Daniel Große, Lucas Klemmer, and Dominik Bonora. Using formal verification methods for optimization of circuits under external constraints. In Design, Automation and Test in Europe Conference (DATE), pages 1–6, 2024. [ bib | DOI | .pdf ]
[5] Lucas Klemmer and Daniel Große. Towards a highly interactive design-debug-verification cycle. In Asia and South Pacific Design Automation Conference (ASP-DAC), pages 692–697, 2024. [ bib | DOI | .pdf ]
[6] Lucas Klemmer, Dominik Bonora, and Daniel Große. Large-scale gatelevel optimization leveraging property checking. In IEEE Design and Verification Conference and Exhibition Europe (IEEE DVCon Europe), pages 86–93, 2023. [ bib | .pdf ]
[7] Frans Skarman, Lucas Klemmer, Oscar Gustafsson, and Daniel Große. Enhancing compiler-driven HDL design with automatic waveform analysis. In Forum on Specification and Design Languages (FDL), pages 1–8, 2023. [ bib | DOI | .pdf ]
[8] Lucas Klemmer and Daniel Große. A DSL for visualizing pipelines: A RISC-V case study. In RISC-V Summit Europe, 2023. [ bib | .pdf ]
[9] Lucas Klemmer, Eyck Jentzsch, and Daniel Große. Programmable analysis of RISC-V processor simulations using WAL. In Design and Verification Conference and Exhibition Europe (DVCon Europe), 2022. [ bib | .pdf ]
[10] Lucas Klemmer, Sonja Gurtner, and Daniel Große. Formal verification of SUBLEQ microcode implementing the RV32I ISA. In Forum on Specification and Design Languages (FDL), pages 1–8, 2022. (Best Paper Award). [ bib | DOI | sourcecode | .pdf ]
[11] Lucas Klemmer and Daniel Große. An exploration platform for microcoded RISC-V cores leveraging the one instruction set computer principle. In IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pages 38–43, 2022. [ bib | DOI | sourcecode | .pdf ]
[12] Lucas Klemmer, Manfred Schlägl, and Daniel Große. RVVRadar: a framework for supporting the programmer in vectorization for RISC-V. In ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 183–187, 2022. [ bib | DOI | sourcecode | .pdf ]
[13] Lucas Klemmer and Daniel Große. Waveform-based performance analysis of RISC-V processors: late breaking results. In Design Automation Conference (DAC), pages 1404–1405, 2022. [ bib | DOI | .pdf ]
[14] Lucas Klemmer and Daniel Große. WAL: a novel waveform analysis language for advanced design understanding and debugging. In Asia and South Pacific Design Automation Conference (ASP-DAC), pages 358–364, 2022. [ bib | DOI | website | sourcecode | .pdf ]
[15] Lucas Klemmer and Daniel Große. EPEX: processor verification by equivalent program execution. In ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 33–38, 2021. [ bib | DOI | .pdf ]
[16] Lucas Klemmer, Saman Froehlich, Rolf Drechsler, and Daniel Große. XbNN: Enabling CNNs on edge devices by approximate on-chip dot product encoding. In IEEE International Symposium on Circuits and Systems (ISCAS), pages 1–5, 2021. [ bib | DOI | .pdf ]
[17] Saman Froehlich, Lucas Klemmer, Daniel Große, and Rolf Drechsler. ASNet: Introducing approximate hardware to high-level synthesis of neural networks. In IEEE International Symposium on Multi-Valued Logic (ISMVL), pages 64–69, 2020. [ bib | DOI | .pdf ]

Workshops

[18] Lucas Klemmer and Daniel Große. WSVA: a SystemVerilog Assertion to WAL compiler. In Workshop on Open-Source Design Automation, 2024. [ bib | .pdf ]
[19] Lucas Klemmer, Sonja Gurtner, and Daniel Große. How we learned to stop worrying and build a RISC-V VP with only one microcode instruction. In ITG/GI/GMM-Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen” (MBMV), 2023. [ bib | .pdf ]
[20] Lucas Klemmer and Daniel Große. Programming language assisted waveform analysis: A case study on the instruction performance of SERV. In Workshop on Open-Source Design Automation, 2023. [ bib | .pdf ]
[21] Lucas Klemmer and Daniel Große. Programmable waveform analysis using the domain specific language WAL. In ITG/GI/GMM-Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen” (MBMV), 2022. [ bib ]

Others

[22] Daniel Große and Lucas Klemmer. Unleash the full potential of your waveforms: From extra-functional analysis to functional debug via programs on waveforms. In Tutorial at DVCon Europe, 2024. [ bib ]
[23] Daniel Große and Lucas Klemmer. Get the most out of your waveforms – from non-functional analysis to functional debug via programs on waveforms. In Tutorial at Forum on specification & Design Languages, 2023. [ bib ]
[24] Sonja Gurtner, Lucas Klemmer, Mathias Fleury, and Daniel Große. Replacing RISC-V instructions by others. In Proc. of SAT Competition 2023 – Solver and Benchmark Descriptions, 2023. [ bib ]
[25] Lucas Klemmer and Daniel Große. Applying the four-eyes principle to RISC-V processor verification by equivalent program execution. In 4th Workshop on RISC-V Activities, 2021. [ bib ]
[26] Lucas Klemmer and Daniel Große. Programmable waveform analysis using WAL. In OpenTapeOut Conference, 2021. [ bib ]