Institute for Complex Systems

Welcome to the Institute for Complex Systems

The Institute for Complex Systems (ICS) targets the ever-increasing complexity of hardware/software systems. Here, the institute considers suitable abstraction levels, i.e. Virtual Prototypes (VPs) in SystemC for HW/SW systems at the Electronic System Level (ESL), HW designs in Verilog/VHDL at the Register Transfer Level (RTL), down to the gate-level. Primary research areas are verification, debugging, and synthesis, all major problems in Electronic Design Automation (EDA). We heavily use the RISC-V Instruction Set Architecture (ISA) in our research work (see e.g. our open-source RISC-V VP++).

Announcements

  • We are looking for Student Assistants. If you are interested, please contact Prof. Daniel Große.

News

2026

2025

  • Dec 15, 2025: Daniel Große has been appointed as Program Committee Member of the Design Automation and Test in Europe (DATE) 2026 PhD Forum.
  • Dec 3, 2025: Daniel Große gave a presentation at the SystemC AMS & COSEDA User Group Meeting 2025 on “RISC-V VP++: Fast Open-Source Virtual Platforms – Powering Research Innovation and Industrial Use”.
  • Oct 20, 2025: Simon Reitinger successfully completed his Master Thesis on “DANUBE: Augments for Hardware Design”. Congratulations!
  • Oct 16, 2025: Daniel Große gave a presentation at the SystemC Evolution Day (SCED) 2025 on “Bringing CHERI Capabilities to Life in a Virtual Platform: CHERI-RISC-V VP++”.
  • Oct 15, 2025: Daniel Große has been appointed as Research Chair of the Design and Verification Conference in Europe (DVCon Europe) 2026.
  • Oct 15, 2025: Christoph Hazott took 3rd place at the DVCon Europe 2025 SystemC Modeling Challenge. Congratulations!
  • Oct 14, 2025: Our work on Leveraging RISC-V for flexible and adaptive real-time radar sequencing is presented at the Design and Verification Conference and Exhibition Europe (DVCon) 2025.
  • Oct 09, 2025: Andreas Hinterdorfer successfully completed his Master Thesis on “CHERI-RISC-V VP++: A Virtual Prototyping Platform Enabling Fine-Grained Memory Protection”. Congratulations!
  • Sep 29, 2025: Tobias Kathan successfully completed his Bachelor thesis entitled “A Web-Based Instruction Decoder with Semantic Explanations for RISC-V”. Congratulations!
  • Sep 26, 2025: Christoph Hazott successfully defends his PhD thesis titled “Breaking Barriers in HW-to-SW Stack Verification” — Congratulations! Many thanks to the examination committee consisting of Prof. Daniel Große (JKU), Prof. Daniel Müller-Gritschneder (TU Wien), Prof. Andreas Springer (JKU) and headed by Prof. Josef Küng (JKU).
  • Sep 18, 2025: Felix Roithmayr successfully completed his Master Thesis on “Securing RISC-y computing with Goldcrest”. Congratulations!
  • Sep 10-12, 2025: Our works on (i) ProtoLens: dynamic transaction visualization in virtual prototypes and (ii) LLM-assisted metamorphic testing of embedded graphics libraries are presented at the Forum on specification & Design Languages (FDL) 2025. Moreover, Christoph Hazott presents his work on “Breaking Barriers in HW-to-SW Stack Verification” at the FDL PhD Forum.
  • Sep 01-04, 2025: Our work on Refined notions of QBF equivalences is presented at the European Conference on Logics in Artificial Intelligence (JELIA) 2025.
  • Aug 08-10, 2025: Felix Roithmayr, member of KuK Hofhackerei - a team of Austrian security professionals and students from JKU, FH St. Pölten, TU Graz, TU Wien, and the University of Vienna - helped secure 9th place at the 2025 final of DEF CON Capture The Flag in Las Vegas. The qualitification was in April where the team had already proven their strength by ranking 6th out of roughly 1,300 international teams.
  • Jul 21-25, 2025: Our work on Surfer – an extensible waveform viewer is presented at the International Conference on Computer Aided Verification (CAV) 2025.
  • Jun 16, 2025: Thomas Schrott successfully completed his Bachelor thesis entitled “Design and Verification of Interrupt Support in a Single-Cycle RISC-V Processor”. Congratulations!
  • Jun 11-13, 2025: Our work on Control flow protection by cryptographic instruction chaining is presented at the International Conference on Security and Cryptography (SECRYPT) 2025.
  • Jun 03, 2026: Daniel Große has been appointed as Program Committee Member of the Design Automation and Test in Europe (DATE) 2026.
  • May 12-15, 2025: Our work on FastISS RISC-V VP++: A simulation performance evaluation of RVV workloads is presented at the RISC-V Summit Europe 2025.
  • May 7, 2025: Daniel Große has been appointed as Topic Co-Chair for “Validation, Verification, Debug and Diagnosis” at the European Test Symposium (ETS) 2026.
  • May 5-7, 2025: Our work on Boosting sw development efficiency with function lifetime diagrams is presented at the IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) 2025.
  • Mar 31-Apr 2, 2025: Our work on Fast interpreter-based instruction set simulation for virtual prototypes is presented at the Design, Automation and Test in Europe (DATE) 2025. The new techniques are already available in our RISCV-VP++ at our ICS GitHub.
  • Mar 11-12, 2025: Our works on (i) RVVTS: A modular, open-source framework for positive and negative testing of the RISC-V “V” vector extension (RVV) and (ii) Towards non-intrusive SystemC checkpointing for digital virtual prototypes are presented at the ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) 2025.
  • Mar 07, 2025: Our book Versatile Hardware Analysis Techniques - From Waveform-based Analysis to Formal Verification has been published by Springer.
  • Mar 04, 2025: Daniel Große has been appointed as Program Committee Member of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) 2025.
  • Feb 13, 2025: Christian Dattinger successfully completed his Bachelor thesis entitled “Visualization of Transaction-Level Model Simulations in Surfer”. Congratulations!
  • Feb 08, 2025: Daniel Große has been appointed as Program Committee Member of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2025.
  • Feb 03, 2025: Jonas Reichhardt successfully completed his Bachelor thesis entitled “ProtoLens: Visualizing Transaction Dynamics in Virtual Prototypes”. Congratulations!
  • Jan 21, 2025: Daniel Große has been appointed as Program Committee Member of the special session “MATTERV: Opensource Methods, architectures, tools and technologies for RISC-V” at the Euromicro Conference Series on Digital System Design (DSD) 2025.
  • Jan 10, 2025: Daniel Große has been appointed as Program Committee Member of the RISC-V Summit Europe 2025.