Newsarchive

News Archive

2022

Dec 22, 2022: Daniel Große has been appointed as Co-Program Chair of the GMM/ITG/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) 2023. Please submit your work!
Dec 15, 2022: Jakob Engblom featured our paper on Programmable analysis of RISC-V processor simulations using WAL in his blog DVCon Europe 2022. Verification, System Simulation, and People!.
Dec 13, 2022: Amiq listed our paper Programmable analysis of RISC-V processor simulations using WAL as one of the Highlights of DVCon EU 2022.
Dec 12, 2022: Sonja Gurtner successfully completed her Master Thesis entitled “A Formally Verified Reduction of the RV32I ISA”. Congratulations!
Dec 7, 2022: Our works on (i) Programmable analysis of RISC-V processor simulations using WAL and (ii) A cross-domain heterogeneous ABV-library for mixed-signal virtual prototypes in SystemC/AMS are presented at the Design and Verification Conference and Exhibition Europe (DVCon Europe 2022).
Oct 20, 2022: Our work on Divider verification using symbolic computer algebra and delayed don’t care optimization is presented at the conference on Formal Methods in Computer-Aided Design (FMCAD 2022).
Sep 23, 2022: The code of our paper SpinalFuzz: Coverage-guided fuzzing for SpinalHDL designs is now available at our ICS GitHub.
Sep 22, 2022: Our work Towards System-level Assertions for Heterogeneous Systems is presented at the International Workshop on Boolean Problems (IWSBP 2022).
Sep 16, 2022: We received the Best Paper Award for our paper Formal verification of SUBLEQ microcode implementing the RV32I ISA at the Forum on specification & Design Languages (FDL 2022). See also our implementation at our ICS GitHub.
Sep 14-16, 2022: We are organizing the 25th IEEE Forum on specification & Design Languages (FDL) in Linz. Screenshot of the FDL 2022 website when starting the conference.
Sep 14, 2022: Our work Formal verification of SUBLEQ microcode implementing the RV32I ISA is presented at the 25th IEEE Forum on specification & Design Languages (FDL 2022).
Sep 6, 2022: Our book Enhanced Virtual Prototyping for Heterogeneous Systems has been published by Springer.
Aug 30, 2022: Amiq mentioned our Waveform Analysis Language (WAL) in their Blog Recommended Articles – August 2022.
Jul 25, 2022: Daniel Große has been appointed as Program Committee Member of the Design Automation and Test in Europe (DATE) 2023.
Jul 25, 2022: Updates on WAL, our Waveform Analysis Language: a) The language documentation is online at wal-lang.org and b) WAL now supports the FST file format and can analyze waveforms with a size of multiple GB. See our ICS GitHub to get the latest version.
Jul 23, 2022: Program of the 25th IEEE Forum on specification & Design Languages (FDL) in Linz from September 14-16, 2022 is out: Technical Program. Our institute hosts FDL this year. Accept our invitation and join us in Linz!
Jul 10-14, 2022: Our works on (i) Late breaking results: Waveform-based performance analysis of RISC-V processors, (ii) Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability and (iii) Verifying SystemC TLM peripherals using modern C++ symbolic execution tools are presented at the Design Automation Conference (DAC 2022).
Jul 4, 2022: Our work An exploration platform for microcoded RISC-V cores leveraging the one instruction set computer principle is presented at the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2022).
Jun 6, 2022: Our works on (i) RVVRadar: a framework for supporting the programmer in vectorization for RISC-V and (ii) Efficient cross-level processor verification using coverage-guided fuzzing are presented at the ACM Great Lakes Symposium on VLSI (GLSVLSI 2022). RVVRadar is also available at our ICS GitHub.
May 25, 2022: Our work SpinalFuzz: Coverage-guided fuzzing for SpinalHDL designs is presented at the European Test Symposium (ETS 2022).
May 16, 2022: Manfred Schlägl successfully completed his Bachelor thesis entitled “RVVRadar - A Framework for Supporting the Programmer in Vectorization for RISC-V”. Congratulations!
May 13, 2022: Daniel Große gave the talk Intelligente Elektronik der Zukunft: Sicherheit durch offene Architekturen und virtuelle Prototypen at the Internationale Akademie Traunkirchen.
Apr 26, 2022: Daniel Große has been appointed as Program Committee Member of the 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) 2022.
Apr 19, 2022: Daniel Große has been appointed as Program Committee Member of the International Workshop on Boolean Problems (IWSBP) 2022.
Mar 2, 2022: Daniel Große has been appointed as Program Committee Member of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2022.
Feb 17, 2022: Our work on “Programmable waveform analysis using the domain specific language WAL” is presented at the ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2022). We have recorded an ASCII cast using WAL to determine the number of cycles SERV and VexRiscv need to execute one instruction on average.
Feb 10, 2022: Gabriel Guldner successfully completed his Bachelor thesis entitled “KHDL - A Typesafe HDL in Kotlin”. Congratulations!
Jan 19, 2022: Our work on WAL: a novel waveform analysis language for advanced design understanding and debugging is presented at the Asia and South Pacific Design Automation Conference (ASP-DAC 2022). WAL is also available at our ICS GitHub.
Jan 10, 2022: Daniel Große has been appointed as the new head of the LIT Secure and Correct Systems Lab.
Jan 8, 2022: Daniel Große has been appointed as Program Committee Member of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2022.
Jan 6, 2022: First Call for Paper for the 25th IEEE Forum on specification & Design Languages (FDL) in Linz from September 14-16, 2022 is out. Our institute hosts FDL this year. Please plan to submit. Download CFP here.

2021

Dec 2, 2021: Our work on “Applying the Four-Eyes Principle to RISC-V Processor Verification by Equivalent Program Execution” is presented at the 4th Workshop on RISC-V Activities.
Nov 6, 2021: Lucas Klemmer talked about “Programmable Waveform Analysis using WAL” at the OpenTapeOut Conference 2021. Underlying paper on the Waveform Analysis Language (WAL) will appear at Asia and South Pacific Design Automation Conference (ASP-DAC 2022). WAL is also available at our ICS GitHub.
Oct 13, 2021: Daniel Große has been appointed as Program Committee Member of the GMM/ITG/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) 2022.
Oct 6, 2021: The Call for Papers for the ACM Transactions on Embedded Computing Systems (ACM TECS) Special Issue on Specification and Design Languages is out. I am Guest Edtior together with Julien Deantoni and Alain Girault.
Oct 6, 2021: Our work on Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level is presented at the International Conference on Very Large Scale Integration (VLSI-SoC 2021).
Oct 4, 2021: Daniel Große gave his inaugural lecture.
Sep 10, 2021: Daniel Große has been appointed as General Chair of the Forum on specification & Design Languages (FDL) 2022. FDL will come to Linz in 2022!
Jun 23, 2021: Our formal RISC-V ISA model used in EPEX: processor verification by equivalent program execution is now online at our ICS GitHub.
Jun 22, 2021: Our work on EPEX: processor verification by equivalent program execution is presented at the ACM Great Lakes Symposium on VLSI (GLSVLSI 2021).
May 24, 2021: Daniel Große has been appointed as Program Committee Member of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2021.
May 26, 2021: Our work on XbNN: Enabling CNNs on edge devices by approximate on-chip dot product encoding is presented at the IEEE International Symposium on Circuits and Systems (ISCAS 2021).
May 4, 2021: Our paper RevSCA-2.0: SCA-based Formal Verification of Non-trivial Multipliers using Reverse Engineering and Local Vanishing Removal has been accepted for publication in the journal IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).
Apr 26, 2021: Our book Recent Findings in Boolean Techniques has been published by Springer.
Apr 23, 2021: Our paper Towards RISC-V CSR Compliance Testing has been accepted for publication in the journal IEEE Embedded Systems Letters.
Mar 31, 2021: Our work on Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform has been accepted in the Journal of Systems Architecture (JSA 2021).
Mar 20, 2021: Our research in the DFG-funded project VerA on formal verification of multiplier and divider circuits using Symbolic Computer Algebra has been covered in an article by Die Presse entitled Forschungsfrage: Rechnet der Computer immer richtig? and by JKU Do Computers Always Perform Correct Calculations?
Mar 18-19, 2021: Our works on “VP-based DIFT for embedded binaries: A RISC-V case study” and “GenMul: Generating architecturally complex multipliers to challenge formal verification tools” will be presented at the ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2021).
Feb 1-5, 2021: Our works on (i) Verifying dividers using symbolic computer algebra and don’t care optimization and (ii) System level verification of phase-locked loop using metamorphic relations (Best Paper Candidate) are presented at the Design, Automation and Test in Europe (DATE 2021).
Jan 28, 2021: Daniel Große has been appointed as Program Committee Member of the 29th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) 2021.
Jan 18-21, 2021: Our works on (i) System-level verification of linear and non-linear behaviors of RF amplifiers using metamorphic relations and (ii) Mutation-based compliance testing for RISC-V are presented at the Asia and South Pacific Design Automation Conference (ASP-DAC 2021).
Jan 7, 2021: Daniel Große has been appointed as Program Committee Member of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021.

2020

Dec 9, 2020: Our work on Closing the RISC-V Compliance Gap via Fuzzing is presented at the RISC-V Summit 2020.
Nov 17, 2020: Our work on Clustering-guided SMT(LRA) learning is presented at the International Conference on integrated Formal Methods (iFM 2020).
Nov 9, 2020: Our work on ASNet: Introducing approximate hardware to high-level synthesis of neural networks is presented at the International Symposium on Multiple-Valued Logic (ISMVL 2020).
Oct 27, 2020: Daniel Große speaks in the tutorial “Cross-Level Compliance Testing and Verification for RISC-V” at the Design and Verification Conference and Exhibition Europe (DVCon 2020).
Oct 22, 2020: Our book Enhanced Virtual Prototyping: Featuring RISC-V Case Studies has been published by Springer.
Oct 20-21, 2020: Our work on RVX - A Tool for Concolic Testing of Embedded Binaries Targeting RISC-V Platforms is presented at the International Symposium on Automated Technology for Verification and Analysis (ATVA 2020).
Oct 20, 2020: Daniel Große has been appointed as Program Committee Member of the Design Automation Conference (DAC) 2021.
Oct 20, 2020: Our work on Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime is presented at the International Conference on Computer Design (ICCD 2020).
Oct 15, 2020: Daniel Große has been appointed as Program Committee Member of the GMM/ITG/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) 2021.
Sep 17, 2020: We received the Best Paper Award for our paper Efficient cross-level testing for processor verification: A RISC-V case-study at the Forum on specification & Design Languages (FDL 2020).
Sep 17, 2020: Daniel Große has been appointed as Program Chair of the Forum on specification & Design Languages (FDL) 2021.
Sep 9-10, 2020: Our works on (i) Early Verification of ISA Extension Specifications using Deep Reinforcement Learning and (ii) Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes are presented at the ACM Great Lakes Symposium on VLSI (GLSVLSI 2020).
Jul 20-24, 2020: Our works on (i) Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side, (ii) Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes and (iii) Verification for Field-coupled Nanocomputing Circuits are presented at the Design Automation Conference (DAC 2020).